6A Digital Integrated Synchronous Step-Down DC/DC
Regulator with Auto Compensation
ZL2102
The ZL2102 is an integrated digital power regulator with auto
compensation and power management functions in a small
package, resulting in a flexible and integrated solution which
can be configured using the Power Navigator graphical user
interface. This synchronous buck converter operates from a
4.5V to 14V input supply and provides from 0.54V to 5.5V
output voltage at up to 6A.
The ZL2102 can be configured for most applications using only
hardware pin straps to adjust switching frequency, output
voltage, UVLO, soft start ramp/delay settings, sequencing
options, and SMBus address. For more advanced
configurations, the ZL2102 supports over 70 PMBus
commands. Output voltage/current is factory calibrated.
Internal synchronous power MOSFETs enable the ZL2102 to
deliver continuous loads up to 6A with high efficiency. An
internal Schottky bootstrap diode reduces discrete component
count. The ZL2102 also supports phase spreading to reduce
system input capacitance.
The ZL2102 uses the SMBus™ with PMBus™ protocol for
communication with a host controller and the Zilker's
proprietary Digital-DC bus for interoperability between other
Zilker Labs devices.
Features
• Integrated MOSFET Switches
• 6A Continuous Output Current
• Adjustable 0.54V to 5.5V Output Range
• 4.5V to 14V Input Range
• Up to 90% Efficiency
• Auto Compensation for Fast Transient Response
• SMBus Compliant Serial Interface
• Snapshot™ Parametric Capture
• Internal Non-Volatile Memory
• Small footprint QFN Package (6mm x 6mm)
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
Related Literature
•
AN2010
"Thermal and Layout Guidelines for Digital-DC™
Products"
•
AN2035
"Compensation Using CompZL™"
•
TB389
"PCB Land Pattern and Surface Mount Guidelines for
QFN Packages"
DDC Bus
INTERFACE
SMBus
DDC
SCL
SDA
SALRT
PG
ZL2102
V2P5
VRA
VR
VDDS
VDDP
10µF
4.7µF
4.7µF
HARDWARE
CONTROL
MGN
EN
BST
C
B
0.1µF
V
IN
12V
C
IN
100µF
L
OUT
2.2µH
V
OUT
3.3V
6A
C
OUT
200µF
SYNC
VSET
HARDWARE
CONFIG
SA
FC
CFG
SS
SW
VSEN
PGND
SGND
DGND
ePAD
FIGURE 1. TYPICAL APPLICATION DIAGRAM
August 22, 2013
FN8440.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas LLC 2013. All Rights Reserved.
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ZL2102
Table of Contents
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital-DC Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Conversion Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Device Address Selection (SA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage and VOUT_MAX Selection (VSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Loop Compensation (FC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization and Sequencing Configuration Settings (CFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency Setting (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start and UVLO Settings (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Over Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Volatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Snapshot™ Parametric Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Train Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Goal Trade-offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
12
12
13
13
14
14
15
15
15
15
15
16
16
16
16
17
17
17
17
17
17
18
18
18
18
19
PCB Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PMBus Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PMBus Command Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2
FN8440.1
August 22, 2013
ZL2102
FIGURE 2. BLOCK DIAGRAM
ZL2102
(36 LD 6X6 QFN)
TOP VIEW
EN
MGN
DDC
V2P5
VRA
VR
VDDS
VDDP
VDDP
36
35
34
33
32
31
30
29
PG
DGND
SYNC
VSET
SA
SCL
SDA
SALRT
FC
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
27
ZL2102
36-Pin QFN
6 x 6 mm
26
25
24
23
22
Exposed Paddle
Connect to SGND
21
20
19
VDDP
BST
SW
SW
SW
SW
SW
SW
PGND
3
CFG
SS
DNC
VSEN
SGND
PGND
PGND
PGND
PGND
FN8440.1
August 22, 2013
ZL2102
Pin Description
PIN NUMBER PIN NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15, 16, 17,
18, 19
20, 21, 22,
23, 24, 25
26
27, 28, 29
30
31
32
33
34
35
36
ePad
PG
DGND
SYNC
VSET
SA
SCL
SDA
SALRT
FC
CFG
SS
DNC
VSEN
SGND
PGND
SW
BST
VDDP
VDDS
VR
VRA
V2P5
DDC
MGN
EN
SGND
TYPE
Output
Ground
DESCRIPTION
Power-good indicator output pin. This pin transitions high after the output voltage stabilizes within the
regulation band. Selectable open drain or push-pull output. Default is open drain.
Digital ground. This is the common return for digital signals. Connect to low impedance ground plane.
Multi-Mode Clock synchronization I/O pin. Used to set switching frequency of internal clock or for synchronization to an
external clock, depending on the setting of the CFG pin. Configured during startup by pin strap.
Multi-Mode Output voltage select pin. Used to set V
OUT
set-point and V
OUT
max. Configured during startup by pin strap.
Multi-Mode Serial address select pin. Used to assign a unique SMBus address to the device. Configured during startup by
pin strap.
I/O
I/O
Output
Serial clock pin for SMBus communication. Connect to external host interface. A pull-up resistor is required for
operation.
Serial data pin for SMBus communication. Connect to external host interface. A pull-up resistor is required for
operation.
Serial alert output pin for SMBus communication. Connect to external host interface if desired.
Multi-Mode Auto compensation configuration pin. Used to set up auto compensation configuration. Configured during
startup by pin strap.
Multi-Mode Configuration pin. Used to configure the SYNC pin and sequencing options. Configured during startup by pin
strap.
Multi-Mode Soft-start pin. Sets the ramp delay/ramp time and UVLO. Configured during startup by pin strap.
No-Connect Do not connect to pin. Leave floating.
Input
Ground
Ground
Output
Input
Power
Power
Power
Power
Power
I/O
Input
Input
Ground
Output voltage positive feedback sense pin.
Common return for analog signals. Connect to low impedance ground plane at one point directly at PGND pins.
Power ground. Common return for internal switching MOSFETs and external Cin/Cout. Connect to low
impedance ground plane.
Output switch node to the inductor.
Boosted floating driver supply pin. The bootstrap capacitor connects from the switch node to this pin.
Supply voltage for internal switching MOSFETs.
Supply voltage for the IC.
Regulated bias from internal 7V low-dropout regulator. Decouple with a 4.7μF capacitor to GND. Not for use with
external circuits.
Regulated bias from internal 5V low-dropout regulator for internal analog circuitry. Decouple with a 4.7μF
capacitor to GND. Not for use with external circuits.
Regulated bias from internal 2.5V low-dropout regulator for internal digital circuitry. Decouple with a 10uF
capacitor to GND. Connect the device's multi-mode pins to this supply pin for logic HIGH pin strap settings.
Digital-DC Bus pin. Allows interoperability between other Zilker Labs devices. A pull-up resistor is required for
operation.
Margin setting pin, used to enable margining of the output voltage. Logic HIGH sets the device to margin high,
logic LOW sets the device to margin low, and leaving the pin floating sets the device to nominal voltage output.
Enable pin, used to enable the output. Default is active high.
Exposed thermal pad. Common return for analog signals. Connect to low impedance ground plane.
4
FN8440.1
August 22, 2013
ZL2102
Ordering Information
PART NUMBER
ZL2102ALAFTK
NOTES:
1. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ZL2102.
For more information on MSL, please see tech brief
TB363.
PART MARKING
2102
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(Pb-free)
36 Ld Exposed Pad 6x6 QFN
PKG.
DWG. #
L36.6x6C
5
FN8440.1
August 22, 2013
Domestic Chip Exchange
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