The ZR36016 accepts input pixels in a variety of common color
spaces. The pixel data can undergo format and color space con-
version, with converted data available on the pixel output bus
(Figure 1). When compressing, the data fed to the ZR36050 can
be cropped within a selected window area, and its format can be
different from that of the pixel output bus. For instance, it is
possible to output an RGB(4:4:4) input onto the pixel output bus
and to feed the ZR36050 with a YbCr(4:2:2) format. It is also
possible to output a YCbCr(4:2:2) format input as RGB(4:4:4)
and to feed the ZR36050 with a YCbCr(4:1:1) format. During
expansion, for instance, the ZR36016 can output an RGB(4:4:4)
input directly onto the output pixel bus, and after converting YCb-
Cr(4:2:2) format coming from the ZR36050 into RGB(4:4:4), it
overlays it in a window on the pixel input data.
The ZR36016 uses an external SRAM double-strip buffer for
raster-block conversions and block interleaving. The Fast
Preview and Lossless modes of operation of the ZR36050 are
also supported, in which case the SRAM is used only for raster-
to-raster buffering and pixel interleaving. Depending on the
SRAM size and the mode of operation, the maximum line length
can be up to 64K pixels. The number of lines per image can be
up to 64K.
Processing of data on the pixel buses can be continuous as
required for live frame capture or Motion JPEG, or it can be dis-
continuous, with pixels transferred only when enabled by an
enable signal.
The data transfer rate with the ZR36050 is at a maximum of
30 MHz, the system clock rate. The pixel buses transfer at a
maximum of 30 MHz for 4:0:0, or at a frequency ratio of 1, 1/2 or
1/4 of the system clock for the other formats, depending on the
format conversions that are selected.
As shown in Figure 2, the input pixel data pass through a multi-
plexer, to the color space convertor. In compression, this
multiplexer always passes the pixel data (the top input). The
output of the color space convertor takes two paths in compres-
sion, one to the pixel output bus and the other to the raster to
block convertor. The data on each path can independently
undergo format conversion, which in this context means a reso-
lution transformation by decimation or interpolation, of the
chrominance components; for example, decimation from
PXIN
Color Space Conversion
Format Conversion
Window Management
Raster-to-Block
ZR36050
Compression
PXOUT
PXIN
Color Space Conversion
Format Conversion
Window Management
Block-to-Raster
ZR36050
Expansion
PXOUT
Figure 1. ZR36016 Operations with a ZR36050
ZORAN Corporation
s
1705 Wyatt Drive
s
Santa Clara, CA 95054
s
(408) 986-1314
s
FAX (408) 986-1240
July 1995
This document was created with FrameMaker 4.0.4
Integrated Color Space / Raster-To-Block Converter
YCrCb(4:4:4) to YCrCb(4:2;2). Format convertor #2 can perform
decimation or interpolation of chrominance, while format conver-
tor #1 can perform decimation in compression. In addition, data
passing through format convertor #1 to the raster to block con-
vertor can be decimated globally by 2, vertically and/or
horizontally, to implement half-screen or quarter-screen
compression.
In expansion, format convertor #2 can perform global horizontal
and/or vertical interpolation, as well as interpolation of chromi-
nance components. Its output is multiplexed with the pixel input
bus, so that the pixel output bus contains the expanded data
within a window on the input data. The color space convertor is
switched in or out as required, simultaneously with the multiplex-
ing of its input, so that the color space of the expanded data is
independent of that of the input.
By means of the delay element shown, the processing pipeline
delay from pixel input to output is kept constant even when color
space conversion is bypassed. The input horizontal and vertical
synchronization signals are output after undergoing an identical
delay.
The mode of operation of the ZR36016 and operating parame-
ters are determined by the control registers, which are
programmed from the host interface. There are two modes of
controlling compressions and expansions: single frame mode
and sequential mode. In the single frame mode, the ZR36016
performs the desired process on a single frame (or field in case
of interlaced motion video) and goes idle until explicitly com-
manded to perform another process. In sequential mode, a new
process starts automatically every frame or field if enabled. The
sequential mode is most suitable for motion JPEG.
VIN
HIN
Delay
MUX
PXIN
Color Space
Converter
MUX
DATA
ADD
RD
WR
CS
Format
Converter #1
Control
Registers
MUX
Delay
Format
Converter #2
VOUT
HOUT
SYSCLK
PXCLK
PXEN
PXOUT
PXOE
START
RESET
FBSY
WINDOW
CBSY
MDATA
Sub-Buffer
Raster/Block Converter
MADD
MWE
MOE
COMP
STOP
BDATA
DSYNC
EOS
Figure 2. ZR36016 Block Diagrams
2
Integrated Color Space / Raster-To-Block Converter
SIGNAL DESCRIPTIONS
Table 1: PIXEL Input/Output
Signal
PXIN[23:0]
PXOUT[23:0]
PXOE
HIN
VIN
HOUT
VOUT
PXEN
I/O
I
O
I
I
I
O
O
I
Pixel data input bus.
Pixel data output bus.
PXOUT bus output enable.
Horizontal input data enable. Rising edge indicates beginning of scan line and start of NAX and PAX counts. For
synchronization of PXIN.
Vertical input data enable. Rising edge indicates beginning of picture and start of NAY and PAY counts. For synchro-
nization of PXIN.
Horizontal output data enable. Follows HIN by internal processing delay. For synchronization of PXOUT.
Vertical output data enable. Follows VIN by internal processing delay. For synchronization of PXOUT.
Pixel enable for PXIN and PXOUT. For discontinuous transfers.
Description
Table 2: Host Interface
Signal
ADD[1:0]
DATA[7:0]
WR
RD
CS
CBSY
I/O
I
I/O
I
I
I
I
Internal registers address input.
Internal registers data bus.
Write enable to internal registers. Written to on rising edge.
Read enable for internal registers.
Chip select for host interface.
CODEC busy. Indicates that the pixel side is ready to exchange strip buffers, but the ZR36050 side is not ready yet.
Description
Table 3: Strip Buffer Memory Interface
Signal
MDATA[15:0]
MADD[15:0]
MWE
MOE
I/O
I/O
O
O
O
Memory data bus for strip buffer.
Memory address for strip buffer.
Memory write enable for strip buffer.
Memory output enable for reading strip buffer.
Description
Table 4: ZR36050 Interface
Signal
BDATA[7:0]
DSYNC
STOP
EOS
COMP
[1]
I/O
I/O
I/O
I/O
I/O
I
Block data bus, connected to ZR36050 PIXEL bus.
Block data synchronization with ZR36050.
Data flow control with ZR36050.
End of scan control with ZR36050.
Compression/expansion mode indicator from ZR36050.
Description
1. The state of the COMP pin determines the direction of the bidirectional pins BDATA, DSYNC, STOP, and EOS. When COMP is high (the ZR36050 is in compression
mode), BDATA, DSYNC and EOS are outputs and STOP is an input. When COMP is low (the ZR36050 is in expansion mode), BDATA, DSYNC and EOS are inputs
and STOP is an output.
3
Integrated Color Space / Raster-To-Block Converter
Table 5: System Interface
Signal
WINDOW
FBSY
START
SYSCLK
PXCLK
RESET
[1]
I/O
O
O
I
I
I
I
Indicates data is within window area.
Frame busy. Indicates processing of frame.
Starts processing with the rising edge in single frame mode, or enables sequential mode.
System clock. ZR36050 bus is synchronous with this clock.
Pixel clock. HIN, VIN and PXIN are synchronous with this clock on input. HOUT, VOUT, PXOUT and WINDOW are
synchronous with this clock on output.
Initial hard reset. Must be held low for 8 SYSCLK cycles. Internal state remains reset for two sysclk cycles after
releasing RESET.
Description
1. When RESET is active, HOUT, VOUT, CBSY, MWE and MOE are driven high, WINDOW, FBSY and MADD are driven low, PXOUT is unaffected (depends on PXIN
and PXOE as usual), DATA is unaffected (depends on CS and RD as usual), and BDATA, DSYNC, STOP, and EOS depend on COMP as usual.
FUNCTIONAL DESCRIPTION
Control Registers
The internal control registers of the ZR36016 are shown in
Figure 3. The access to these registers is through the host inter-
face. Access to the Mode, Address Pointer and Configuration
Tables is possible only when the ZR36016 is idle or when FBSY
is not asserted. However, it is always possible to access the GO/
STOP register.
There are four byte-wide direct access registers and twelve
byte-wide indirect access registers.
Bit 0
ADD[1:0]
00
01
10
11
Direct Access Registers
GO/STOP
Mode
Address Pointer
Indirect Data
(Read/Write)
Address Pointer
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
Indirect Access Registers
Set Registers 1 & 2
(Read/Write)
GO/STOP Register
Read/Write
Initial Value
Function
Direct address: 0x00
0x00
Register to enable and stop processing by the
ZR36016.
7
6
5
4
3
–
2
–
1
–
0
GO/
STOP
Version Number
GO/STOP
: Processing enable and stop bit.
Initial value = 0.
0= Terminates the processing.
1= Enables processing.
Window Area Registers
(Read/Write)
Number of Lines Register
(Read Only)
A 1 in the GO/STOP bit, in concert with the START
signal, enables processing by the ZR36016. Once
the GO/STOP bit has been set, processing will be
enabled when START is high. For compression the
actual processing period starts with the following
rising edge of VIN and for expansion with the first
DSYNC. Clearing the GO/STOP bit at any time
prevents the start of any future processing.
In the single frame mode the GO/STOP bit is
cleared automatically after the single frame has
been processed, and it must be set again to process
a new frame.
In the sequential mode, when GO is set it remains
set but the processing period can be controlled with
the START signal.
Bits 1-3
Reserved.
Bits 4-7 Version Number:
The version number of the
ZR36016.
These bits contain the version number. Values start
at 0 and increment for each silicon step. Read only.
Figure 3. Control Registers
Access to the indirect registers uses the Address Pointer direct
register. Its loaded value is used to point to the location from
which accesses start in the indirect registers. For example, to
write starting from the top of the Window Area Registers section,
write 0x02 in the Address Pointer register and after that write the
data in the Indirect Data register. After the first write to the
Address Pointer register, the address pointer is incremented
automatically after each access of the Indirect Data register. The
Address Pointer register stops incrementing at 0x0B, even if the
host continues to access the Indirect Data register.
4
Integrated Color Space / Raster-To-Block Converter
Mode Register
Read/Write
Initial Value
Function
Direct address: 0x01
0x91
Determines the basic operating modes and formats
of the ZR36016.
7
CMPR
6
DSPY
5
4
3
2
MODE
1
0
Mode Register (Continued)
Bits 5-6
DSPY: Determines the PXOUT bus output formats.
Initial Value = 0x00.
Setting this field of the Mode register selects the
output data format of the PXOUT bus, for each
format of the PXIN bus as selected by the MODE
field of the register, as shown in the table below.
DSPY
PXIN Bus Image Format
[1]
4:4:4
(RGB)
4:4:4
(YCbCr)
4:2:2
(YCbCr)
4:1:1
(Philips)
PXOUT
is 4:1:1
(Philips)
1:0:0
PXOUT
is 1:0:0
4:4:4:4
PXOUT
is 4:4:4
Bit 0-4
MODE
: Determines the PXIN input and ZR36050
image formats and color spaces. Initial Value =
0x11.
ZR36050 Image Format
Input (Compression)
Output (Expansion)
Image
Format
4:4:4
4:2:2
4:1:1 (H2V2)
4:0:0
4:4:4
Reserved
4:4:4
YCbCr
4:4:4
4:2:2
4:1:1 (H2V2)
4:0:0
4:4:4
Reserved
4:2:2
YCbCr
4:2:2
4:1:1 (H2V2)
4:0:0
Reserved
4:1:1
(PHILIPS)
YCbCr
4:1:1 (H4V1)
4:0:0
Reserved
4:4:4:4
–
4:4:4:4
Reserved
1:0:0
–
1:0:0
Reserved
–
–
YCbCr
Y Only
YCbCr
YCbCr
Y Only
YCbCr
YCbCr
YCbCr
Y Only
RGB
Color Space
YCbCr
YCbCr
YCbCr
Y Only
RGB
Bit
6
Bit
5
0
0
1
1
0
1
0
1
PXOUT is 4:4:4 (RGB)
PXOUT is 4:4:4 (YCbCr)
PXOUT is 4:2:2 (YCbCr)
Reserved
PXBIN Bus
MODE
(HEX)
00
01
02
03
[1]
04
05~07
08
09
0A
0B
[1]
0C
0D~10
11
12
13
[1]
Image
Format
4:4:4
Color
Space
RGB
1. The image format conversions implied by this table
are performed by Format Converter #2 in the block
diagram.
Bit 7
CMPR: Selects compression or expansion
Initial Value = 1
0 = Expansion Mode.
1 = Compression Mode.
Setup Register 1
Read/Write
Initial Value
Indirect address: 0x00
0x01
7
CKRT
6
5
4
HRFL
3
DSFL
2
SBFL
1
RSTR
0
CNTI
VERT HORZ
14, 15
16
17
[1]
18
19
1A
1B
1C~1F
Bit 0
CNTI
: Single-Frame/Sequential processing
selection.
Initial value = 1.
0= Single Frame Mode. Processes the image enabled
by VIN and then enters an idle state. For process-
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