Automotive PSoC
®
4: PSoC 4200M
Family Datasheet
Programmable System-on-Chip (PSoC
®
)
Automotive PSoC
®
4: PSoC 4200M Family Datasheet
, Programmable System-on-Chip (PSoC
®
)
General Description
PSoC
®
4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
Arm
®
Cortex™-M0 CPU, while being AEC-Q100 compliant. It combines programmable and reconfigurable analog and digital blocks
with flexible automatic routing. The PSoC 4200M product family, based on this platform architecture, is a combination of a
microcontroller with digital programmable logic, programmable analog, programmable interconnect, high-performance
analog-to-digital conversion, opamps with comparator mode, and standard communication and timing peripherals. The PSoC 4200M
products will be fully compatible with members of the PSoC 4 platform for new applications and design needs. The programmable
analog and digital subsystems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Subsystem
Automotive Electronics Council (AEC) AEC-Q100 qualified
■
48 MHz Arm Cortex-M0 CPU with single-cycle multiply
■
Up to 128 kB of flash with Read Accelerator
■
Up to 16 kB of SRAM
■
DMA engine
■
Segment LCD Drive
■
■
LCD drive supported on all pins (common or segment)
Operates in Deep Sleep mode with 4 bits per pin memory
Four independent run-time reconfigurable serial
communication blocks (SCBs) with reconfigurable I
2
C, SPI,
UART, or LIN Slave functionality
Two independent CAN blocks for automotive networking
Eight 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
48-pin, 64-pin TQFP, and 56-QFN packages
Up to 51 programmable GPIOs
GPIO pins can be CapSense, LCD, analog, or digital
Drive modes, strengths, and slew rates are programmable
Grade-A: –40 °C to +85 °C
Grade-S: –40 °C to +105 °C
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
Applications Programming Interface (API component) for all
fixed-function and programmable peripherals
After schematic entry, development can be done with
ARM-based industry-standard development tools
Serial Communication
■
Programmable Analog
Four opamps that operate in Deep Sleep mode at very low
current levels
■
All opamps have reconfigurable high current pin-drive,
high-bandwidth internal drive, ADC input buffering, and
Comparator modes with flexible connectivity allowing input
connections to any pin
■
Four current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■
Two low-power comparators that operate in Deep Sleep mode
■
12-bit SAR ADC with 1-Msps conversion rate
■
■
Timing and Pulse-Width Modulation
■
■
■
Package Options
■
■
■
■
Programmable Digital
Four programmable logic blocks, each with 8 Macrocells and
an 8-bit data path (called universal digital blocks or UDBs)
■
Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
■
Temperature Range
■
■
Low Power 1.71 to 5.5 V Operation
20-nA Stop Mode with GPIO pin wakeup
■
Hibernate and Deep Sleep modes allow wakeup-time versus
power trade-offs
■
PSoC Creator Design Environment
■
Capacitive Sensing
Cypress Capacitive Sigma-Delta (CSD) technique provides
best-in-class SNR (>5:1) and water tolerance
■
Cypress-supplied software component makes capacitive
sensing design easy
■
Automatic hardware tuning (SmartSense™)
■
■
Industry-Standard Tool Compatibility
■
Cypress Semiconductor Corporation
Document Number: 002-09829 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 29, 2019
Automotive PSoC
®
4: PSoC 4200M
Family Datasheet
More Information
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP.
Following is an abbreviated list for PSoC 4:
■
■
■
Overview:
PSoC Portfolio, PSoC Roadmap
Product Selectors:
PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
❐
AN79953:
Getting Started With PSoC 4
❐
AN88619:
PSoC 4 Hardware Design Considerations
❐
AN86439:
Using PSoC 4 GPIO Pins
❐
AN57821:
Mixed Signal Circuit Board Layout
❐
AN81623:
Digital Design Best Practices
❐
AN73854:
Introduction To Bootloaders
❐
AN89610:
ARM Cortex Code Optimization
■
Technical Reference Manual (TRM) is in two documents:
❐
Architecture TRM
details each PSoC 4 functional block.
❐
Registers TRM
describes each of the PSoC 4 registers.
■
Development Kits:
❐
CY8CKIT-042,
PSoC 4 Pioneer Kit, is an easy-to-use and
inexpensive development platform. This kit includes
connectors for Arduino™ compatible shields and Digilent
®
Pmod™ daughter cards.
❐
CY8CKIT-049
is a very low-cost prototyping platform. It is a
low-cost alternative to sampling PSoC 4 devices.
❐
CY8CKIT-001
is a common development platform for any
one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP families
of devices.
The
MiniProg3
device provides an interface for flash
programming and debug.
PSoC Creator
PSoC Creator
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the
list of component datasheets.
With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator Contents
1
2
3
5
4
Document Number: 002-09829 Rev. *E
Page 2 of 42
Automotive PSoC
®
4: PSoC 4200M
Family Datasheet
Contents
PSoC 4200M Block Diagram ............................................ 4
Functional Definition ........................................................ 5
CPU and Memory Subsystem ..................................... 5
System Resources ...................................................... 5
Analog Blocks .............................................................. 6
Programmable Digital .................................................. 7
Fixed Function Digital .................................................. 8
GPIO ........................................................................... 9
Special Function Peripherals ....................................... 9
Pinouts ............................................................................ 10
Power ............................................................................... 14
Unregulated External Supply ..................................... 14
Regulated External Supply ........................................ 14
Development Support .................................................... 15
Documentation .......................................................... 15
Online ........................................................................ 15
Tools .......................................................................... 15
Electrical Specifications ................................................ 16
Absolute Maximum Ratings ...................................... 16
Device Level Specifications ....................................... 16
Analog Peripherals .................................................... 20
Digital Peripherals ..................................................... 25
Memory ..................................................................... 27
System Resources .................................................... 28
Ordering Information ...................................................... 32
Ordering Code Definitions ......................................... 33
Packaging ........................................................................ 34
Acronyms ........................................................................ 37
Document Conventions ................................................. 39
Units of Measure ....................................................... 39
Revision History ............................................................. 40
Sales, Solutions, and Legal Information ...................... 41
Worldwide Sales and Design Support ....................... 41
Products .................................................................... 41
PSoC® Solutions ...................................................... 41
Cypress Developer Community ................................. 41
Technical Support ..................................................... 41
Document Number: 002-09829 Rev. *E
Page 3 of 42
Automotive PSoC
®
4: PSoC 4200M
Family Datasheet
PSoC 4200M Block Diagram
CPU Subsystem
PSoC 4200M
32-bit
SWD /TC
SPCIF
Cortex
M0
48 MHz
FAST MUL
NVIC, IRQMX
FLASH
128 KB
Read Accelerator
SRAM
16 KB
SRAM Controller
ROM
8 KB
ROM Controller
DataWire/
DMA
Initiator / MMIO
AHB- Lite
System Resources
Power
Sleep Control
WIC
POR
LVD
REF
BOD
PWRSYS
NVLatches
Clock
Clock Control
WDT
IMO
ILO
System Interconnect (Multi Layer AHB)
Peripherals
PCLK
Peripheral Interconnect (MMIO)
Programmable
Analog
Programmable
Digital
UDB
...
UDB
4x SCB-
I2C/SPI/UART
IOSS GPIO
(8x ports)
2x LP Comparator
2x Capsense
8x TCPWM
2x CAN
Reset
Reset Control
XRES
Test
DFT Logic
DFT Analog
x1
x4
SMX
CTBm
2x Opamp
x2
Port Interface & Digital System Interconnect (DSI)
Power Modes
Active / Sleep
Deep Sleep
Hibernate
High Speed I/O Matrix
49 x GPIO, 6 x GPIO_ OVT
I/O Subsystem
The PSoC 4200-M devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial_Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator Integrated Development Environment (IDE)
provides fully integrated programming and debug support for
PSoC 4200-M devices. The SWD interface is fully compatible
with industry-standard third-party tools. The PSoC 4200-M
family provides a level of security not possible with multi-chip
application solutions or with microcontrollers. This is due to its
ability to disable debug features, robust flash protection, and
because it allows customer-proprietary functionality to be imple-
mented in on-chip programmable blocks.
The debug circuits are enabled by default and can only be
disabled in firmware. If not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. Because all programming, debug, and test
interfaces are disabled when maximum device security is
enabled, PSoC 4200-M with device security enabled may not be
returned for failure analysis. This is a trade-off the PSoC 4200-M
allows the customer to make.
Document Number: 002-09829 Rev. *E
LCD
SAR ADC
(12-bit)
Page 4 of 42
WCO
Automotive PSoC
®
4: PSoC 4200M
Family Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in the PSoC 4200-M is part of the 32-bit
MCU subsystem, which is optimized for low-power operation
with extensive clock gating. Most instructions are 16 bits in length
and execute a subset of the Thumb-2 instruction set. The
Cypress implementation includes a hardware multiplier that
provides a 32-bit result in one cycle. It includes a nested vectored
interrupt controller (NVIC) block with 32 interrupt inputs and also
includes a Wakeup Interrupt Controller (WIC), which can wake
the processor up from the Deep Sleep mode allowing power to
be switched off to the main processor when the chip is in the
Deep Sleep mode. The Cortex-M0 CPU provides a
Non-Maskable Interrupt (NMI) input, which is made available to
the user when it is not in use for system functions requested by
the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG; the debug
configuration used for PSoC 4200-M has four break-point
(address) comparators and two watchpoint (data) comparators.
Flash
The PSoC 4200-M has a flash module with a flash accelerator,
tightly coupled to the CPU to improve average access times from
the flash block. The flash accelerator delivers 85% of
single-cycle SRAM access performance on average. Part of the
flash module can be used to emulate EEPROM operation if
required.
SRAM
SRAM memory is retained during Hibernate.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
DMA
A DMA engine, with eight channels, is provided that can do 32-bit
transfers and has chainable ping-pong descriptors.
clk_lf
Clock System
The PSoC 4200-M clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that no meta-stable conditions occur.
The clock system for the PSoC 4200-M consists of a Watch
Crystal Oscillator (WCO) running at 32 kHz, the IMO (3 to
48 MHz) and the ILO (32-kHz nominal) internal oscillators, and
provision for an external clock.
Figure 2. PSoC 4200M MCU Clocking Architecture
IMO
clk_hf
clk_ext
dsi_in[0]
dsi_in[1]
dsi_in[2]
dsi_in[3]
dsi_out[3:0]
ILO
The clk_hf signal can be divided down to generate synchronous
clocks for the UDBs, and the analog and digital peripherals.
There are a total of 16 clock dividers for the PSoC 4200-M, each
with 16-bit divide capability; this allows 12 to be used for the
fixed-function blocks and four for the UDBs. The analog clock
leads the digital clocks to allow analog events to occur before
digital clock-related noise is generated. The 16-bit capability
allows a lot of flexibility in generating fine-grained frequency
values and is fully supported in PSoC Creator.
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4200M. It is trimmed during testing to achieve the
specified accuracy. Trim values are stored in nonvolatile
memory. Trimming can also be done on the fly to allow in-field
calibration. The IMO default frequency is 24 MHz and it can be
adjusted between 3 to 48 MHz in steps of 1 MHz. IMO tolerance
with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power oscillator, nominally 32 kHz, which
is primarily used to generate clocks for peripheral operation in
Deep Sleep mode. ILO-driven counters can be calibrated to the
IMO to improve accuracy. Cypress provides a software
component, which does the calibration.
Crystal Oscillator
The PSoC 4200M clock subsystem also includes a
low-frequency crystal oscillator (32-kHz WCO) that is available
during the Deep Sleep mode and can be used for Real-Time
Clock (RTC) and Watchdog Timer applications.
System Resources
Power System
The power system is described in detail in the section
Power on
page 14.
It provides assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (brown-out
detect (BOD)) or interrupts (low voltage detect (LVD)). The
PSoC 4200M operates with a single external supply over the
range of 1.71 to 5.5 V and has five different power modes, transi-
tions between which are managed by the power system. The
PSoC 4200M provides Sleep, Deep Sleep, Hibernate, and Stop
low-power modes.
Document Number: 002-09829 Rev. *E
Page 5 of 42
ADI Reference Circuit
京公网安备 11010802033920号
EEWORLD
