20D201K datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> 20D201K

Preview

20D201K: DescriptionVDR（Voltage Dependent Resistor）; CategoryPassive components; File Size366KB，3 Pages; ManufacturerSPSEMI; Websitehttp://www.spsemi.cn

Download Datasheet View All

20D201K Overview

VDR（Voltage Dependent Resistor）

Preview

Download Datasheet

View All

20D Series

Varistor Type MYG

Type MYG Varistors are made of semiconductor ceramic materials composed mainly of

zinc oxide. They have non-linear resistance that changes as a function of applied voltage. It has

small size, high current capacity, and high protection level.

Features

Recommended Applications

　　　　　　＞

Protection of semiconductors

Surge protection of consumer equipment

Surge protection of communication, measuring or controller instrument

Relay or electromagnetic Valve surge absorption

Wide Varistor voltage range (18V½１８００V)

Excellent non-linearity and protection level

Large withstanding surge current

Fast response（≤20ns）

Explanation of Part Numbers

Element Size

20mm

Varistor Voltage

The first two digits are

ignificant figures and the

third one denotes number of

zeros following

Voltage

Tolerance

K:±10%

Dimension

Range of voltage

(V)

max

Dimensions(mm)

max

min

d±

0.1

D1±1.0

18 - 68

82 - 1800

23.0

23.5

4.1~5.5 25

4.8~15.5 25

1.0

10.0

REV.2014.05.01

01 | www.spsemi.cn

Recommended Resources

AD694 functional schematic diagram

Programmable timing circuit composed of TC4013 and analog switch TC4066

Timer circuit that displays time using light dots

Unijunction transistor directly triggers thyristor circuit

Computer motherboard circuit diagram 820 2_41

PS Learning Tutorial: ...; 张召庆 Integrated technical exchanges

Privileged Classmate 2020 Video Tutorial "Learning Verilog by Coding (FPGA Tools and Syntax)": B station video collection: https://www.bilibili.com/video/BV1Ve411x75W?from=searchseid=71364886936769315Whether it is digital IC design or FPGA development, Verilog is the most basic and important ne...; ove学习使我快乐 FPGA/CPLD

Can you guys help me see if this thing can be done with CPLD?: B in the figure is the ADC sampling chip, the sampling rate is 500K, each sampling value is 16 bits, and the ADC interface is a three-wire SPI interface.There are 10 ADCs in total. To combine the samp...; dsp_comm FPGA/CPLD

Motor current sampling: [Ask if you don't understand] This is a partial circuit diagram of a motor driver that I recently came across. What I don't understand is [1] The output in the diagram is the current of one phase from...; shaorc Integrated technical exchanges

Is it better to use the EMIF port or the HPI port of the DSP to transmit data from FPGA to DSP?: The data collected by AD is transmitted to FPGA, and then FPGA transmits it to DSP (TMS320C6416T). The data rate required for transmission is 12MByte/s.The DSP board is a development board from Hezhon...; dsp_comm FPGA/CPLD

Application of solid state relays in servo motors: Introduces the basic principles of solid-state relays and their applications in servo motors...; frozenviolet Industrial Control Electronics

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components