74LVC240A
Octal buffer/line driver with 5 V tolerant inputs/outputs;
inverting; 3-state
Rev. 8 — 29 November 2011
Product data sheet
1. General description
The 74LVC240A is an octal inverting buffer/line driver with 3-state outputs. The 3-state
outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes
the outputs to assume a high-impedance OFF-state. Schmitt trigger action at all inputs
makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V or 5 V applications.
The 74LVC240A is functionally identical to the 74LVC244A except that the 244 has
non-inverting outputs.
2. Features and benefits
5 V tolerant inputs for interlacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC240A
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC240AD
74LVC240ADB
40 C
to +125
C
40 C
to +125
C
Name
SO20
SSOP20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
Type number
74LVC240APW
40 C
to +125
C
74LVC240ABQ
40 C
to +125
C
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
4. Functional diagram
2
1A0
1Y0
18
4
1A1
1Y1
16
6
1A2
1Y2
14
1
8
EN
18
16
14
12
15
17
1
1A3
1Y3
12
2
2
17
4
15
6
13
8
11
1
19
1A0
2A0
1A1
2A1
1A2
2A2
1A3
2A3
1OE
2OE
mgu779
1OE
1Y0 18
2Y0 3
1Y1 16
2Y1 5
4
6
8
2A0
2Y0
3
2A1
2Y1
5
19
1Y2 14
2Y2
7
11
1Y3 12
2Y3 9
13
15
17
EN
9
7
5
3
mgu778
13
2A2
2Y2
7
11
2A3
2Y3
9
19
2OE
mgu780
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Functional diagram
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
2 of 17
NXP Semiconductors
74LVC240A
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
5. Pinning information
5.1 Pinning
1OE
2
3
4
5
1
terminal 1
index area
1A0
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
1
2
3
4
5
6
7
8
9
20 V
CC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
11 2A3
001aad036
20 V
CC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
2A3 11
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
240
6
7
8
9
GND 10
GND
(1)
240
GND 10
001aad037
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO20 and (T)SSOP20
Fig 5.
Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
1OE
2OE
1A[0:3]
2A[0:3]
1Y[0:3]
2Y[0:3]
GND
V
CC
Pin description
Pin
1
19
2, 4, 6, 8
17, 15, 13, 11
18, 16, 14, 12
3, 5, 7, 9
10
20
Description
output enable input (active LOW)
output enable input (active LOW)
data input
data input
data output
data output
ground (0 V)
power supply
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
3 of 17
NXP Semiconductors
74LVC240A
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
6. Functional description
Table 3.
Inputs
nOE
L
L
H
[1]
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high-impedance OFF-state
Function selection
[1]
Output
nAn
L
H
X
nYn
H
L
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0
output HIGH or LOW state
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO20 packages: above 70
C
derate linearly with 8 mW/K.
For (T)SSOP20 packages: above 60
C
derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
C
derate linearly with 4.5 mW/K.
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
4 of 17
NXP Semiconductors
74LVC240A
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
output HIGH or LOW state
output 3-state
in free air
input transition rise and fall V
CC
= 1.65 V to 2.7 V
rate
V
CC
= 2.7 V to 3.6 V
Conditions
Min
1.65
1.2
0
0
0
40
0
0
Typ
-
-
-
-
-
-
-
-
Max
3.6
-
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
V
C
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level
input voltage
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output
voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
18
mA; V
CC
= 3.0 V
I
O
=
24
mA; V
CC
= 3.0 V
V
OL
LOW-level
output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
input leakage V
CC
= 3.6 V; V
I
= 5.5 V or GND
current
-
-
-
-
-
-
-
-
-
-
-
0.1
0.2
0.45
0.6
0.4
0.55
5
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
20
V
V
V
V
V
A
V
CC
0.2
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
-
-
V
CC
0.3
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
-
V
V
V
V
V
V
40 C
to +85
C
Min
1.08
0.65
V
CC
1.7
2.0
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.12
0.35
V
CC
0.7
0.8
40 C
to +125
C
Min
1.08
0.65
V
CC
1.7
2.0
-
-
-
-
Max
-
-
-
-
0.12
0.7
0.8
V
V
V
V
V
V
V
Unit
0.35
V
CC
V
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
5 of 17
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