• SerDes associated with unused ports are turned-off
• SerDes associated with unused lanes are placed in a low
power state
32 General Purpose I/O
Reliability, Availability and Serviceability (RAS)
ECRC support
AER on all ports
SECDED ECC protection on all internal RAMs
End-to-end data path parity protection
Checksum Serial EEPROM content protected
Autonomous link reliability (preserves system operation in the
presence of faulty links)
–
Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
Test and Debug
–
On-chip link activity and status outputs available for Port 0
(upstream port)
–
Per port link activity and status outputs available using
external I
2
C I/O expander for all other ports
–
SerDes test modes
–
Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
Power Supplies
–
Requires only two power supply voltages (1.0 V and 2.5 V)
Note that a 3.3V is preferred for V
DD
I/O
–
No power sequencing requirements
Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with
1mm ball spacing
–
Compatible with IDT 89HPES64H16 PCIe Gen1 switch
Note:
For pin compatibility issues, contact the IDT help desk
at
ssdhelp@idt.com.
–
–
–
–
–
–
Product Description
Utilizing standard PCI Express interconnect, the PES64H16G2
provides the most efficient fan-out solution for applications requiring
high throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 64 GBps (512 Gbps) of aggregated,
full-duplex switching capacity through 64 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 GT/s of band-
width in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
The PES64H16G2 is based on a flexible and efficient layered archi-
tecture. The PCI Express layer consists of SerDes, Physical, Data Link
and Transaction layers in compliance with PCI Express Base specifica-
tion Revision 2.0. The PES64H16G2 can operate either as a store and
forward or cut-through switch. It supports eight Traffic Classes (TCs)
and one Virtual Channel (VC) with sophisticated resource management
to enable efficient switching and I/O connectivity for servers, storage,
and embedded processors with limited connectivity.
The PES64H16G2 is a
partitionable
PCIe switch. This means that in
addition to operating as a standard PCI express switch, the
PES64H16G2 ports may be partitioned into groups that logically
operate as completely independent PCIe switches. Figure 2 illustrates a
three partition PES64H16G2 configuration.
2 of 57
November 28, 2011
IDT 89HPES64H16G2 Data Sheet
Block Diagram
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
Route Table
Port
Arbitration
16-Port Switch Core
Frame Buffer
Scheduler
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
SerDes
SerDes
SerDes
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
64 PCI Express Lanes
Up to 8 x8 ports or 16 x4 Ports
Figure 1 Internal Block Diagram
Partition 1
Upstream Port
Partition 2
Upstream Port
Partition 3
Upstream Port
P2P
Bridge
P2P
Bridge
P2P
Bridge
Partition 1 – Virtual PCI Bus
Partition 2 – Virtual PCI Bus
Partition 3 – Virtual PCI Bus
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
Partition 1
Downstream Ports
Partition 2
Downstream Ports
Partition 3
Downstream Ports
Figure 2 Example of Usage of Switch Partitioning
3 of 57
November 28, 2011
IDT 89HPES64H16G2 Data Sheet
SMBus Interface
The PES64H16G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES64H16G2,
allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration
register values of the PES64H16G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is
also used by an external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Table 1.
Bit
1
2
3
4
5
6
7
Slave
SMBus
Address
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
0
SSMBADDR[5]
1
1
Master
SMBus
Address
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
1
0
1
Table 1 Master and Slave SMBus Address Assignment
As shown in Figure 3, the master and slave SMBuses may only be used in a split configuration.
Switch
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
Hot-Plug
I/O
Expander
Figure 3 Split SMBus Interface Configuration
4 of 57
November 28, 2011
IDT 89HPES64H16G2 Data Sheet
The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the SMBus
lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two independent
buses; thus, multi-master arbitration is not required.
Hot-Plug Interface
The PES64H16G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
PES64H16G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES64H16G2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES64H16G2. In response to an I/O expander interrupt, the PES64H16G2 generates an
SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES64H16G2 provides 32 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO
pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables list the functions of the pins provided on the PES64H16G2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
PE00RP[3:0]
PE00RN[3:0]
PE00TP[3:0]
PE00TN[3:0]
PE01RP[3:0]
PE01RN[3:0]
PE01TP[3:0]
PE01TN[3:0]
PE02RP[3:0]
PE02RN[3:0]
PE02TP[3:0]
PE02TN[3:0]
PE03RP[3:0]
PE03RN[3:0]
PE03TP[3:0]
PE03TN[3:0]
PE04RP[3:0]
PE04RN[3:0]
PE04TP[3:0]
PE04TN[3:0]
Type
I
O
I
Name/Description
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive
pairs for port 0.
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 0.
PCI Express Port 1 Serial Data Receive.
Differential PCI Express receive
pairs for port 1. When port 0 is merged with port 1, these signals become
port 0 receive pairs for lanes 4 through 7.
PCI Express Port 1 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 1. When port 0 is merged with port 1, these signals
become port 0 transmit pairs for lanes 4 through 7.
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 3 Serial Data Receive.
Differential PCI Express receive
pairs for port 3. When port 2 is merged with port 3, these signals become
port 2 receive pairs for lanes 4 through 7.
PCI Express Port 3 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 3. When port 2 is merged with port 3, these signals
become port 2 transmit pairs for lanes 4 through 7.
TI technical sales engineers introduce TI's latest AM335x Starter Kit. AM335x Starter Kit is a low-cost development kit that helps developers quickly adopt Sitara ARM Cortex-A8 AM335x processors (AM33...
[i=s]This post was last edited by qwqwqw2088 on 2018-1-10 22:57[/i] [size=4][b]1. Rated current (In)[/b] The rated operating current marked on the fuse. This value is determined by the manufacturer an...
How to develop digital TV under wince6.0, is there any relevant information? Please send me a copy. It would be best if you can provide an idea. Thank you...
Dual MCU master-slave parallel communication interface, the two MCUs are AT89C51 and AT89C2052 respectively. AT89C51 MCU is used as the master MCU, connected through four control signal lines and eigh...
Abstract: This paper introduces the performance and characteristics of the AT89C2051 single-chip microcomputer, and introduces a low-cost, high-precision, miniaturized, digital display car anti-colli...
Tesla and BYD, vying for dominance in the global electric vehicle market, are reportedly considering adopting Samsung's AMOLED (active-matrix organic light-emitting diode) technology for their next...[Details]
Reflow soldering, a common soldering method in modern electronics manufacturing, primarily melts solder paste and pads to form solder joints. With technological advancements, soldering equipment ha...[Details]
introduction
With the development of digital and network technologies, broadcasting technology has become increasingly diversified, with the most significant trend being the transition from an...[Details]
With the rapid development of technology, automotive intelligence is increasing at an unprecedented rate. This not only enhances vehicle functionality and comfort, but also places higher deman...[Details]
According to foreign media reports, researchers at the University of Surrey have developed an artificial intelligence system that can accurately locate the location of equipment in densely populate...[Details]
Core point: The automotive industry chain and the humanoid robot industry have collaborative advantages in hardware, software, and scenarios. Upstream and downstream companies in the automotive ind...[Details]
Based on a survey of more than ten intelligent robot companies, this article sorts out and analyzes the current development status of the intelligent industry and the challenges and differences it ...[Details]
In June 2014, the Ministry of Industry and Information Technology issued 4G FD-LTE licenses to China Unicom and China Telecom. Together with the 4G TD-LTE licenses issued to China Mobile, China Uni...[Details]
Overview
As handheld voice communication devices become more and more popular, they are increasingly used in noisy environments, such as airports, busy roads, crowded bars, etc. In such noisy ...[Details]
Pure electric vehicles, structurally speaking, have components such as a power battery. In addition to the power battery, a small battery also powers some low-voltage electrical components and even...[Details]
With the advent of the electric car era, the number of pure electric vehicles has increased significantly, but many car owners do not know how to properly maintain pure electric vehicles. In additi...[Details]
Intel®
Xeon®
6
-
core processors now support the new Amazon EC2 R8i and R8i-flex instances on Amazon Web Services (AWS).
These new instances offer superior performance and fast...[Details]
HTTP is the abbreviation of Hypertext Transfer Protocol. It is an application protocol based on TCP/IP communication protocol used to transmit HTML and image files. It is an application-level objec...[Details]
With the support and encouragement of national policies, some Internet car manufacturers have also joined the new energy vehicle manufacturing industry. From the perspective of new car manufacturer...[Details]
The range of an electric vehicle is crucial to the driving experience, and range anxiety is a common headache when driving an electric vehicle. Although the latest electric vehicles can achieve a r...[Details]
DSP and ARM Processors
京公网安备 11010802033920号
EEWORLD
