Datasheet
The 24bit Audio CODEC series
Monaural Audio CODEC
with Touch Panel Interface
BU26154MUV
General Description
BU26154 is a low-power compact audio CODEC.
BU26154 also incorporates touch panel interface and
Cap-Less headphones amplifier, speaker amplifier which
is most suitable for digital still cameras, electronic
dictionaries. BU26154 has built-in voltage regulator for
the stability of CODEC characteristic that is sensitive to
the outside noise. Speaker amplifier that can change AB
/ D Class. Therefore, when the interference including the
FM radio influences it, BU26154 can prevent
interference by operating AB grade. As digital code
processing, it is equipped with the high-pass filter as the
noise cut use of the specific frequency band, Notch filter
2
and the Equalizer of 5 bands and P Bass+, Noise gate,
and flexible sound quality effect processing is possible.
Key Specifications
■
HVDD Power Supply:
SPVDD Power Supply:
CPDD Power Supply:
TVDD Power Supply:
MIC-ADC SNR:
DAC-SP SNR:
DAC-HP SNR t:
2.7V to 3.6V
2.7V to 5.5V
2.7V to 3.6V
2.7V to 3.6V
92dB(Typ)
95dB (Typ)
93dB (Typ)
Package(s)
VQFN040V6060
W (Typ) x D (Typ) x H (Max)
6.00mm x 6.00mm x 0.50mm
Features
■
Various sound processing functions
2
P Bass+
Noise gate
Fast release ALC
5-band Equalizer/Notch Filter
High PSRR is attained by built-in regulator
Speaker amplifier can be switched to AB class and
D class.
Touch panel interface.
■
■
■
VQFN040V6060
Applications
■
■
■
■
■
Electronic Dictionary
Digital Still Camera
Digital Single-lens Reflex Camera
Digital Mirror-less Camera
Digital Video Camera, others
Typical Application Circuit(s)
VMID
HVDD
MBIASCAP
Bias
MICBIAS
REGOUT
REGOUT
MIN1
MIN2
SPVDD
SPGND
SPVDD
SPOUT+
SP
SPOUT-
HPVDD
VOL
HPL
HPCOM
HPR
CPVDD
HPVDD
CPP
CPN
HPVSS
CPGND
XP
XN
YP
YN
TVDD
TGND
IRQB
PLLC
LDO
HP
HPVSS
HPVDD
CHARGE
PUMP
HPVSS
TVDD
TOUCH
PANEL I/F
MCLKI
CLOCK
PLL
IO
TSTO
HP
HPVSS
HPVDD
REGOUT
DAC
REGOUT
DAC
VOL
ALC
Filter
Sound Effect
Serial
Audio
InterFac
e
SAI_LRCLK
IO
SAI_BCLK
SAI_SDOUT
SAI_SDIN
PGA
REGOUT
REGOUT IOVDD
ADC
RESET
Class AB or
Class D
IO
RESETB
CPU
I/F
IO
CSB/SCL
SDATA/SDA
SCLK
LDO
HVDD1 HGND2 REGOUT
HGND1
REGOUT IOVDD
REGOUT IOVDD
REGOUT
IOVDD
Figure 1. Block Diagram
〇Product
structure : Silicon monolithic integrated circuit
.
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〇This
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BU26154MUV
Pin Configuration(s)
Datasheet
Top view
SAI_SDOUT
SAI_LRCLK
SDATA/SDA
SAI_SDIN
SCLK/SAD
SAI_BCLK
CSB/SCL
MCLKI
22
IRQB
30
YP
XP
XN
YN
TGND
TVDD
HPCOM
CPVDD
CPP
HPR
31
32
33
34
35
36
37
38
39
40
1
HPL
29
28
27
26
25
24
23
21
20
19
18
17
16
15
14
13
12
11
RESETB
PLLC
REGOUT
HVDD
NC
HGND1
HGND2
MIN2
MIN1
MBIASCAP
2
HPVDD
3
CPGND
4
HPVSS
5
CPN
6
SPVDD
7
SPOUT+
8
SPOUT-
9
SPGND
10
VMID
Figure 2.
Pin Configuration(s)
Pin Description(s)
No
17
6
38
16
36
15
Name
HVDD
SPVDD
CPVDD
N.C
TVDD
HGND1
I/O
P
P
P
-
P
P
Power
-
-
-
-
-
-
Function
High voltage power supply pin
A capacitor is connected between HVDD and HGND1.
Speaker power supply pin
A capacitor is connected between SPVDD and SPGND.
Voltage power supply pin for charge pump
A capacitor is connected between CPVDD and CPGND.
A no connect pin.
Voltage power supply for the touch panel
Please connect a capacitor between TVDD and TGND.
High voltage ground 1
It is used on the same voltage as HGND2, SPGND,
CPGND, and TGND.
High voltage ground 2
It is used on the same voltage as HGND1, SPGND,
CPGND, and TGND.
Ground pin for Speaker
It is used on the same voltage as HGND1, HGND2,
CPGND, and TGND.
Ground pin for charge pump
It is used on the same voltage as HGND1, HGND2,
SPGND, and TGND.
Ground pin for touch panel interface
It is used on the same voltage as HGND1, HGND2,
CPGND, and SPGND.
Regulator output
A capacitor is connected between REGOUT and HGND1.
Please connect as close as possible to the chip.
Reset
(Note1)
-
-
-
-
-
-
No use
(Note3)
-
-
-
-
-
-
14
HGND2
P
-
TSTO
-
-
9
SPGND
P
-
-
-
3
CPGND
P
-
-
-
35
TGND
P
-
-
-
18
REGOUT
O
HVDD
HGND2
-
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A positive side voltage output pin for the headphones
driver.
A capacitor is connected between HPVDD and CPGND.
Please connect as close as possible to the chip.
A negative side voltage output pin for the headphones
driver.
A capacitor is connected between HPVSS and CPGND.
Please connect as close as possible to the chip.
Master Clock pin
Output pin for test-mode. Make it open.
Reset pin
"L" level: Reset enables.
"H" level: Reset disable.
3 wire interface: data input output pin
It is indicated as SDATA.
2 wire interface: data input output pin
(Note 1)
It is indicated as SDA.
3 wire interface: Serial clock input pin
It is indicated as SCLK.
2 wire interface: Slave address select input pin.
It is indicated as SAD.
SAD pin = "L" level slave address is "0011010"
SAD pin = "H" level slave address is "0011011"
3 wire interface: chip select input pin
It is indicated as CSB.
2 wire interface: Serial clock input pin *1
It is indicated as SCL.
SAI LR clock input/output pin
SAI bit clock input/output pin
SAI serial data input pin
SAI serial data output pin
An interrupt output terminal. When an interrupt occurs,
chip outputs "L".
Analog reference voltage pin
A capacitor is connected between VMID and HGND2.
Microphone bias voltage output pin
A capacitor is connected between HGND2.
Please connect as close as possible to the chip.
Analog microphone input 1
Single-end and differential can be chosen.
When differential is chosen, it connects with microphone
+ pin.
Analog microphone input 2
Single-end and differential can be chosen.
When differential is chosen, it connects with microphone
- pin.
speaker output - pin
speaker output + pin
Headphones output Lch terminal
Headphones output Rch terminal
Charge pump flying capacitor, positive side output pin
Charge pump flying capacitor, negative side output pin
PLL filter pin
When clock of the MCLKI pin input is used, make it open.
When clock of the SAI_BCLK pin input is used, it is
necessary to connect resistors and a capacitor.
YP pin for the touch panel interface
XP pin for the touch panel interface
XN pin for the touch panel interface
YN pin for the touch panel interface
Headphones amplifier common pin
Datasheet
2
HPVDD
O
CPVDD
CPGND
(Note 2)
4
22
21
20
HPVSS
MCLKI
TSTO
RESETB
O
I
O
I
CPVDD
HVDD
HVDD
HVDD
CPGND
(input)
HGND1
(input)
(Note 2)
HGND1
Open
-
24
SDATA
/SDA
IO
HVDD
(input)
-
25
SCLK
/SAD
I
HVDD
(input)
HGND1
23
26
27
28
29
30
10
11
CSB
/SCL
SAI_LRCLK
SAI_BCLK
SAI_SDIN
SAI_SDOUT
IRQB
VMID
MBIASCAP
I
IO
IO
I
O
O
O
O
HVDD
HVDD
HVDD
HVDD
HVDD
HVDD
REGOUT
HVDD
(input)
(input)
(input)
(input)
HGND1
HGND1
HGND2
HGND2
-
HGND1
HGND1
HGND1
Open
Open
-
Open
12
MIN1
I
REGOUT
Hi-Z
Open
13
8
7
1
40
39
5
19
31
32
33
34
37
MIN2
SPOUT-
SPOUT+
HPL
HPR
CPP
CPN
PLLC
YP
XP
XN
YN
HPCOM
I
O
O
O
O
O
O
O
O
O
O
O
I
REGOUT
SPVDD
SPVDD
SPVDD
SPVDD
CPVDD
CPVDD
HVDD
TVDD
TVDD
TVDD
TVDD
-
Hi-Z
SPGND
SPGND
CPGND
CPGND
Hi-Z
Hi-Z
HGND2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
(input)
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
-
(Note 1) In case of 2 wire serial, if this pin is used with external pull-up resistor, it possibly gets noise from power.
in the noisy environment.
(Note 2) At the time of power down, in HPVDD and HPVSS, is short-circuited.
Therefore, tamper noise design is required
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Description of Block(s)
Datasheet
CPVDD HVDD
MBIASCAP
M
IN1
MIN2
TVDD
SPVDD
CSB/SCL
SDATA/SDA
SCLK
RESETB
IRQB
SAI_LRCLK
SAI_BCLK
SAI_SDOUT
SAI_SDIN
MCLKI
PLLC
BU26154
SPOUT+
SPOUT-
CPU
and
DSP
HPL
HPR
VMID
REGOUT
HPVDD
CPP
CPN
HPVSS
XP
XN
YP
YN
Open
Touch
Screen
HPCOM
TSTO
CPGND HGND2HGND1 TGND SPGND
Figure 3. BU26154
Description of Block
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Absolute Maximum Ratings (Ta = 25°C)
(HGND1=HGND2=SPGND=CPGND=TGND=0V)
Parameter
HVDD Supply Voltage
Symbol
HVDD
Condition
-
Rating
-0.3 to 4.5
Unit
V
Datasheet
SPVDD Supply Voltage
SPVDD
-
-0.3 to 7.0
V
CPVDD Supply Voltage
CPVDD
-
MCLKI, SAI_LRCLK,
SAI_BCLK, SAI_SDIN,
SDATA/SDA, SCLK.
CSB/SCL pins
MIN1, MIN2 pins
-
(Note 1)
-0.3 to 4.5
V
Input Voltage
VIN
-0.3 to HVDD+0.3
-0.3 to REGOUT+0.3
-55 to +150
V
V
℃
Storage Temperature
T
stg
Ta=25°C
Power Dissipation
(Note 1)
0.80
W
Pd
Ta=25°C
(Note 2)
3.01
W
Output Current 1
IOSP
SPOUT+, SPOUT- pins
-560 to +560
mA
Output Current 2
IOHP
HPL, HPR pins
HPVSS,HPVDD,CP,CN
pin
REGOUT pin
Except SPOUT+,SPOUT-,
HPL,HPR,
REGOUT,HPVDD,HPVSS
pins
-100 to +100
mA
Output Current 3
IOCP
-500 to +500
mA
Output Current 4
IOREGO
-30 to 0
mA
Output Current 5
IOO
-8 to +8
mA
Do not short the output pin to another output pin, power supply pin or GND pin.(Output pin includes an IO pin which is in output mode)
(Note 1) 74.2mm×74.2mm×1.6tmm FR4 1Layer Glass epoxy base Surface Copper foil 0%)Mounting
Above Ta=25℃,reduced by 8.0mW/℃. Thermal beer is on a base.
(Note 2) 74.2mm×74.2mm×1.6tmm FR4. 4 Layer Glass epoxy base(2,3layer Copper foil 100%)Mounting
Above Ta=25℃, reduced by 30.12mW/℃. Thermal beer is on a base.
Caution:
Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions
(HGND1=HGND2=SPGND=CPGND=TGND=0V)
Parameter
HVDD Supply Voltage
SPVDD Supply Voltage
CPVDD Supply Voltage
TVDD Supply Voltage
Operating Temperature
Symbol
HVDD
SPVDD
CPVDD
TVDD
T
op
Condition
HVDD=CPVDD=TVDD
-
HVDD=CPVDD=TVDD
HVDD=CPVDD=TVDD
-
Rating
2.7 to 3.6
2.7 to 5.5
2.7 to 3.6
2.7 to 3.6
-20 to +85
Unit
V
V
V
V
℃
(Note 1) The radiation-proof design is not carried out.
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