N-Channel Enhancement Mode Field Effect Transistor
FEATURES
650V, 1.8A, R
DS(ON)
= 5.5Ω @V
GS
= 10V.
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handing capability.
Lead free product is acquired.
TO-251 & TO-252 package.
CED02N65G/CEU02N65G
D
D
G
S
CEU SERIES
TO-252(D-PAK)
G
D
G
S
CED SERIES
TO-251(I-PAK)
S
ABSOLUTE MAXIMUM RATINGS
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous @ T
C
= 25 C
@ T
C
= 100 C
Drain Current-Pulsed
a
Tc = 25 C unless otherwise noted
Symbol
V
DS
V
GS
I
D
I
DM
P
D
E
AS
I
AS
T
J
,T
stg
Limit
650
Units
V
V
A
A
A
W
W/ C
mJ
A
C
±
30
1.8
1.1
7.2
48
0.38
11.25
1.5
-55 to 150
Maximum Power Dissipation @ T
C
= 25 C
- Derate above 25 C
Single Pulsed Avalanche Energy
e
Single Pulsed Avalanche Current
e
Operating and Store Temperature Range
Thermal Characteristics
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Symbol
R
θJC
R
θJA
Limit
2.6
50
Units
C/W
C/W
Details are subject to change without notice .
1
Rev 1. 2011.Oct
http://www.cetsemi.com
CED02N65G/CEU02N65G
Electrical Characteristics
Parameter
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics
Static Drain-Source
On-Resistance
Dynamic Characteristics
c
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
b
c
b
Tc = 25 C unless otherwise noted
Symbol
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(on)
Test Condition
V
GS
= 0V, I
D
= 250µA
V
DS
= 650V, V
GS
= 0V
V
GS
= 30V, V
DS
= 0V
V
GS
= -30V, V
DS
= 0V
V
GS
= V
DS
, I
D
= 250µA
V
GS
= 10V, I
D
= 0.9A
2
4.4
Min
650
1
100
-100
4
5.5
Typ
Max
Units
V
µA
nA
nA
V
Ω
Gate Threshold Voltage
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
V
DS
= 25V, V
GS
= 0V,
f = 1.0 MHz
295
75
20
19
11
29
10
6.7
1.5
3
1.8
38
22
58
20
8.9
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
A
V
V
DD
= 300V, I
D
= 1A,
V
GS
= 10V, R
GEN
= 18Ω
V
DS
= 480V, I
D
= 1A,
V
GS
= 10V
Drain-Source Diode Characteristics and Maximun Ratings
V
GS
= 0V, I
S
= 1A
1.5
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Device Mounted on FR4 Board, t < 10 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing.
e.L = 10mH, IAS =1.5A, VDD = 50V, RG = 25Ω, Starting TJ = 25 C
2
CED02N65G/CEU02N65G
3.0
2.5
2.0
1.5
1.0
0.5
0
V
GS
=10,9,8,7V
3.0
T
J
=125C
2.5
2.0
1.5
1.0
0.5
0
25 C
I
D
, Drain Current (A)
V
GS
=6V
V
GS
=5V
I
D
, Drain Current (A)
-55 C
0
2.5
5
7.5
10
12.5
0
5
10
15
20
25
30
V
DS
, Drain-to-Source Voltage (V)
Figure 1. Output Characteristics
900
750
600
450
300
150
0
Coss
Crss
0
5
10
15
20
25
Ciss
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-100
V
GS
, Gate-to-Source Voltage (V)
Figure 2. Transfer Characteristics
I
D
=0.9A
V
GS
=10V
R
DS(ON),
Normalized
R
DS(ON)
, On-Resistance(Ohms)
C, Capacitance (pF)
-50
0
50
100
150
200
V
DS
, Drain-to-Source Voltage (V)
Figure 3. Capacitance
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
-50
V
DS
=V
GS
T
J
, Junction Temperature( C)
Figure 4. On-Resistance Variation
with Temperature
10
1
V
TH
, Normalized
Gate-Source Threshold Voltage
I
S
, Source-drain current (A)
I
D
=250µA
V
GS
=0V
10
0
-25
0
25
50
75
100
125
150
10
-1
0.4
0.6
0.8
1.0
1.2
1.4
1.6
T
J
, Junction Temperature( C)
Figure 5. Gate Threshold Variation
with Temperature
V
SD
, Body Diode Forward Voltage (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
CED02N65G/CEU02N65G
V
GS
, Gate to Source Voltage (V)
10
8
6
4
2
0
V
DS
=480V
I
D
=1A
10
1
R
DS(ON)
Limit
100ms
1ms
10ms
DC
I
D
, Drain Current (A)
10
0
10
-1
0
2
4
6
8
10
-2
T
C
=25 C
T
J
=175 C
Single Pulse
10
0
10
1
10
2
10
3
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
V
DD
t
on
V
IN
V
GS
R
GEN
G
R
L
D
V
OUT
t
d(on)
V
OUT
10%
V
DS
, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
t
off
t
r
90%
t
d(off)
90%
10%
t
f
INVERTED
90%
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
r(t),Normalized Effective
Transient Thermal Impedance
10
0
D=0.5
0.2
10
-1
0.1
0.05
0.02
0.01
Single Pulse
P
DM
t
1
t
2
10
-2
1. R
θJC
(t)=r (t) * R
θJC
2. R
θJC
=See Datasheet
3. T
JM-
T
C
= P* R
θJC
(t)
4. Duty Cycle, D=t1/t2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
Square Wave Pulse Duration (sec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
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