NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500
pieces of “DRV103U/2K5” will get a single 2500-piece Tape and Reel.
NOTES: (1) Output current is limited by internal current limit and by DRV103 power dissipation. (2) Output current resets to zero when current limit is reached.
(3) Logic High enables output (normal operation). (4) Constant DC output to PWM (Pulse-Width Modulated) time. (5) Maximum delay is determined by an external
capacitor. Pulling the Delay Adjust Pin LOW corresponds to an infinite (continuous) delay. (6) Delay to PWM
≈
C
D
• 10
6
(C
D
in
F • 1.1). (7) Connecting the Delay Adjust Pin to +5V reduces delay time to less than 1µs. (8) V
IN
at pin 3 to percent of duty cycle at pin 6. (9) OK Flag LOW indicates
fault from over-temperature or over-current conditions. (10) PowerPAD™ SO-8 (H) package has highest continuous current (2A) because the chip operates at a
lower junction temperature when underside metal tab is connected to a heat sink or heat spreader.
θ
JA
= 68°C/W measured on DRV103 demo board;
θ
JA
= 58°C/W measured on JEDEC standard test board. H package
θ
JC
= 16.7°C/W.
DRV103
SBVS029A
3
PIN CONFIGURATION
Top View
Duty Cycle Adj
Delay Adj
Osc Freq Adj
GND
1
2
3
4
SO
8
7
6
5
Input
Status OK Flag
+V
S
OUT
PIN DESCRIPTIONS
PIN #
Pin 1
NAME
Duty Cycle Adjust
DESCRIPTION
Internally, this pin connects to the input of a comparator and a (2.75 x I
REF
) current source from V
S
. The voltage at this node linearly
sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage, or the voltage output of a D/A converter. The
active voltage range is from 1.3V to 3.9V to facilitate the use of single-supply control electronics. At 3.56V, output duty cycle is near
90%. At 1.5V, output duty cycle is near 10%.
This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results
in a delay of approximately 18µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less than
1µs by tying the pin to 5V. This pin connects internally to a 3µA current source from V
S
and to a 2.6V threshold comparator. When
the pin voltage is below 2.6V, the output device is 100% ON. The PWM oscillator is not synchronized to the Input (pin 1), so the
duration of the first pulse may be any portion of the programmed duty cycle.
PWM frequency is adjustable. A resistor to ground sets the current I
REF
and the internal PWM oscillator frequency. A range of 500Hz
to 100kHz can be achieved with practical resistor values. Although oscillator frequency operation below 500Hz is possible, resistors
higher than 10M will be required. The pin then becomes a very high impedance node and is, therefore, sensitive to noise pickup
and PCB leakage currents.
This pin must be connected to system ground for the DRV103 to function. It carries the 0.4mA quiescent current plus the full load
current when the power DMOS transistor is switched on.
The output is the drain of a power DMOS transistor with its source connected to ground. Its low on-resistance (0.5Ω typ) assures
low power dissipation in the DRV103. Gate drive to the power device is controlled to provide a slew-rate limited rise and fall time.
This reduces radiated RFI/EMI noise. A flyback diode is needed with inductive loads to conduct the load current during the off
cycle. The external diode should be selected for low forward voltage and low storage time. The internal clamp diode (an ESD
protection diode) provides some degree of back-EMF protection but it should not be used as a flyback diode.
This is the power supply pin. Operating range is +8V to +32V. +V
S
must be
≥
the supply voltage to the load.
Normally HIGH (active LOW), a Flag LOW signals either an over-temperature or over-current fault. The over-current flag (Status
OK) is LOW only when the output is ON (constant DC output or the “ON” portion of PWM mode). A thermal fault (thermal shutdown)
occurs when the die surface reaches approximately 160°C and latches until the die cools to 140°C. This output requires a pull-
up resistor and it can typically sink 2mA, sufficient to drive a low-current LED. Sink current is internally limited at 10mA typical.
The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above the
typical switching threshold, 1.7V. Below this level, the output is disabled. Input current is typically 10nA when driven HIGH and 10nA
with the input LOW. The input should not be directly connected to the power supply (V
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