• 1 to 5 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps
• Half-period jitter: 60ps
• CYCLE - CYCLE jitter 40ps
• OUTPUT - OUTPUT skew: 40ps
Pin Configuration
1
A
B
C
D
E
F
2
3
4
5
28-Ball BGA
Top View
Block Diagram
CLKT0
OE
OS
AV
DD
Powerdown
Control and
Test Logic
PLL bypass
LD* or OE
CLKC0
CLKT1
CLKC1
CLKT2
LD*
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
Ball Assignments
1
A
B
C
D
E
CLKT0
CK_INT
CK_INC
AGND
AVDD
CLKC4
2
CLKC0
V
DD
OE
GND
GND
CLKT4
3
CLKC1
NB
V
DD
V
DD
NB
CLKC3
4
CLKT1
V
DD
OS
GND
GND
CLKT3
5
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT2
CLKC2
CLK_INT
CLK_INC
10K-100k
PLL
GND
FB_INT
FB_INC
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
FB_OUTT
FB_OUTC
F
1202—06/30/06
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS97U2A845A
Advance Information
Pin Descriptions
Te r m i n a l
Name
AGND
AV
DD
CLK_INT
CLK_INC
FB_INT
FB_INC
FB_OUTT
FB_OUTC
OE
OS
GND
V
DDQ
CLKT[0:4]
CLKC[0:4]
NB
Analog Ground
A n a l o g p ow e r
Clock input with a (10K-100K Ohm) pulldown resistor
Complentar y clock input with a (10K-100K Ohm) pulldown resistor
Feedback clock input
Complementary feedback clock input
Feedback clock output
Complementary feedback clock output
Output Enable (Asynchronous)
Output Select (tied to GND or V
DDQ
)
Ground
Logic and output power
Clock outputs
Complementary clock outputs
No ball
Description
Electrical
Characteristics
Ground
1.8 V nominal
Differential input
Differential input
Differential input
Differential input
Differential output
Differential output
LVCMOS input
LVCMOS input
Ground
1.8V nominal
Differential outputs
Differential outputs
The PLL clock buffer,
ICS97U2A845A,
is designed for a V
DDQ
of 1.8 V, a AV
DD
of 1.8 V and differential data input and
output levels. Package options include a plastic 28-ball VFBGA.
ICS97U2A845A
is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five
differential pair of clock outputs (CLKT[0:4], CLKC[0:4]) and one differential pair feedback clock outputs (FB_OUTT,
FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,
FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except
FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output
Select) is a program pin that must be tied to GND or V
DDQ
. When OS is high, OE will function as described above. When
OS is low, OE has no effect on CLKT3/CLKC3 (they are free running in addition to FB_OUTT/FB_OUTC). When AV
DD
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time t
STAB
.
The PLL in
ICS97U2A845A
clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:4], CLKC[0:4]).
ICS97U2A845A
is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97U2A845A
is characterized for operation from 0°C to 70°C.
1202—06/30/06
2
ICS97U2A845A
Advance Information
Function Table
Inputs
AVDD
GND
GND
GND
GND
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
OE
H
H
L
L
L
L
H
H
X
X
OS
X
X
H
L
H
L
X
X
X
X
CLK_INT
L
H
L
H
L
H
L
H
L
H
CLK_INT
H
L
H
L
H
L
H
L
L
H
CLKT
L
H
*L(Z)
*L(Z),
CLKT3
active
*L(Z)
*L(Z),
CLKT3
active
L
H
*L(Z)
CLKC
H
L
*L(Z)
*L(Z),
CLKC3
active
*L(Z)
*L(Z),
CLKC3
active
H
L
*L(Z)
Outputs
PLL
FB_OUTT
L
H
L
H
L
H
FB_OUTC
H
L
H
L
Bypassed/Off
Bypassed/Off
Bypassed/Off
Bypassed/Off
H
L
On
On
L
H
*L(Z)
Reser ved
H
L
*L(Z)
On
On
Off
*L(Z) means the outputs are disabled to a low stated meeting the I
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