IR2010(S)PBF
High and Low Side Driver
Features
Floating channel designed for bootstrap operation
Fully operational to 200V
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
3.3V logic compatible
Separate logic supply range from 3.3V to 20V
Logic and power ground +/-5V offset
CMOS Schmitt-triggered inputs with pull-down
Shut down input turns off both channels
Cross-conduction prevention logic
Matched propagation delay for both channels
Outputs in phase with inputs
Product Summary
V
OFFSET
(max)
I
O+/-
(typ)
V
OUT
t
on/off
(typ)
Delay Matching (max)
200V
3.0A / 3.0A
10 – 20V
95ns & 65ns
15ns
Description
The IR2010 is a high power, high voltage, high speed power
MOSFET and IGBT driver with independent high and low
side referenced output channels. Logic inputs are compatible
with standard CMOS or LSTTL output, down to 3.0V logic.
The output drivers feature a high pulse current buffer stage
designed for minimum driver cross-conduction. Propagation
delays are matched to simplify use in high frequency
applications. The floating channel can be used to drive an N-
channel power MOSFET or IGBT in the high side
configuration which operates up to 200 volts. Proprietary
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction.
Package Options
14-Lead PDIP
16-Lead SOIC
Wide Body
Applications
Converters
DC motor drive
Ordering Information
Base Part Number
IR2010PBF
IR2010SPBF
IR2010SPBF
Standard Pack
Package Type
PDIP14
SO16W
SO16W
Form
Tube
Tube
Tape and Reel
Quantity
25
45
1000
Orderable Part Number
IR2010PBF
IR2010SPBF
IR2010STRPBF
1
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© 2015 International Rectifier
April 14, 2015
IR2010(S)PBF
Typical Connection Diagram
200V
HO
V
DD
HIN
SD
LIN
V
SS
V
DD
HIN
SD
LIN
V
SS
V
CC
COM
LO
V
CC
(Refer to Lead Assignments for correct configuration.) This diagram shows electrical connections only. Please refer to our Application Notes
and Design Tips for proper circuit board layout
V
B
V
S
To Load
2
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© 2015 International Rectifier
April 14, 2015
IR2010(S)PBF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
dV
s
/dt
P
D
Rth
JA
T
J
T
S
T
L
Definition
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side fixed supply voltage
Low side output voltage
Logic supply voltage
Logic supply offset voltage
Logic input voltage (HIN, LIN & SD)
Allowable offset supply voltage transient (figure 2)
14-Lead PDIP
Package power dissipation
@ T
A
≤ +25°C
16-Lead SOIC
14-Lead PDIP
Thermal resistance, junction to
ambient
16-Lead SOIC
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
-0.3
V
CC
- 25
V
SS
- 0.3
—
—
—
—
—
—
-55
—
Max.
225
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+ 0.3
V
SS
+ 25
V
CC
+ 0.3
V
DD
+ 0.3
50
1.6
1.25
75
100
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within
the recommended conditions. The V
S
and V
SS
offset rating is tested with all supplies biased at 15V differential.
Typical ratings at other bias conditions are shown in figures 24 and 25.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
T
A
Definition
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side fixed supply voltage
Low side output voltage
Logic supply voltage
Logic supply offset voltage
Logic input voltage (HIN, LIN, & SD)
Ambient temperature
Min.
V
S
+ 10
†
Max.
V
S
+ 20
200
V
B
20
V
CC
V
SS
+ 20
5
V
DD
125
Units
V
S
10
0
V
SS
+ 3
-5
††
V
SS
-40
V
°C
†
Logic operational for V
S
of -4 to +200V. Logic state held for V
S
of -4V to -V
BS
.
††
When V
DD
< 5V, the minimum V
SS
offset is limited to -V
DD
(Please refer to the Design Tip DT97-3 for more details).
3
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© 2015 International Rectifier
April 14, 2015
IR2010(S)PBF
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15V, C
L
= 1000pF and T
A
= 25°C and V
SS
= COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in figure 3.
Symbol
t
on
t
off
t
sd
t
r
t
f
MT
Definition
Turn-on propagation delay
Turn-off propagation delay
Shutdown propagation delay
Turn-on rise time
Turn-off fall time
Delay matching, HS & LS turn-on/off
Figure
7
8
9
10
11
6
Min.
50
30
35
—
—
—
Typ.
95
65
70
10
15
—
Max.
135
105
105
20
25
15
Units
Test Conditions
V
S
= 0V
V
S
= 200V
ns
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15V and T
A
= 25°C and V
SS
= COM unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to V
SS
and are applicable to all three logic input leads: HIN, LIN and SD. The V
O
and I
O
parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
QDD
I
IN+
I
IN-
V
BSUV+
V
BSUV-
V
CCUV+
V
CCUV-
I
O+
I
O-
Definition
Logic “1” input voltage
Logic “0” input voltage
Logic “1” input voltage
Logic “0” input voltage
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Quiescent V
DD
supply current
Logic “1” input bias current
Logic “0” input bias current
V
BS
supply undervoltage positive
going threshold
V
BS
supply undervoltage negative
going threshold
V
CC
supply undervoltage positive
going threshold
V
CC
supply undervoltage negative
going threshold
Output high short circuit pulsed
current
Output low short circuit pulsed
current
Figure
12
13
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Min.
9.5
—
2
—
—
—
—
—
—
—
—
—
7.5
7.0
7.5
7.0
2.5
2.5
Typ.
—
—
—
—
—
—
—
70
100
1
20
—
8.6
8.2
8.6
8.2
3.0
3.0
Max.
—
6.0
—
1
1.0
0.1
50
210
230
5
40
1.0
9.7
9.4
V
9.7
9.4
—
A
—
V
O
= 0V, V
IN
= V
DD
PW ≤ 10 μs
V
O
= 15V, V
IN
= 0V
PW ≤ 10 μs
Units
Test Conditions
V
DD
= 15V
V
V
DD
= 3.3V
I
O
= 0A
V
B
= V
S
= 200V
μA
V
IN
= 0V or V
DD
V
IN
= V
DD
V
IN
= 0V
4
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© 2015 International Rectifier
April 14, 2015
IR2010(S)PBF
Functional Block Diagram
5
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© 2015 International Rectifier
April 14, 2015
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