IR2213(S)PBF
High and Low Side Driver
Features
Floating channel designed for bootstrap operation
Fully operational to +1200 V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 12 V to 20 V
Undervoltage lockout for both channels
3.3 V logic compatible
Separate logic supply range from 3.3 V to 20 V
Logic and power ground ±5 V offset
CMOS Schmitt-triggered inputs with pull-down
Cycle by cycle edge-triggered shutdown logic
Matched propagation delay for both channels
Outputs in phase with inputs
Product Summary
V
OFFSET
(max)
I
O+/-
V
OUT
t
on/off
(typical)
Delay Matching
1200 V
1.7 A / 2 A
12 V – 20 V
280 ns / 225 ns
30 ns
Description
The IR2213(S) is a high voltage, high speed power
MOSFET and IGBT driver with independent high and low
side referenced output channels. Proprietary HVIC and
latch immune CMOS technologies enable ruggedized
monolithic construction. Logic inputs are compatible with
standard CMOS or LSTTL outputs, down to 3.3 V logic.
The output drivers feature a high pulse current buffer stage
designed
for
minimum
driver
cross-conduction.
Propagation delays are matched to simplify use in high
frequency applications. The floating channel can be used
to drive an N-channel power MOSFET or IGBT in the high
side configuration which operates up to 1200 V.
Package Options
16 Lead SOIC
(Wide Body)
14 Lead PDIP
Ordering Information
Base Part Number
IR2213SPBF
IR2213SPBF
IR2213PBF
Standard Pack
Package Type
SO16WB
SO16WB
PDIP14
Form
Tube
Tape and Reel
Tube
Quantity
45
1000
25
Orderable Part Number
IR2213SPBF
IR2213STRPBF
IR2213PBF
1
www.irf.com
© 2014 International Rectifier
February 4, 2014
IR2213(S)PBF
Typical Connection Diagram
Refer to Lead Assignments for correct pin configuration. This/These diagram(s) show electrical connections
only. Please refer to our Application Notes and Design Tips for proper circuit board layout
2
www.irf.com
© 2014 International Rectifier
February 4, 2014
IR2213(S)PBF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are
measured under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
dVs/dt
P
D
R
THJA
T
J
T
S
T
L
Definition
High Side Floating Supply Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
Allowable Offset Supply Voltage Transient (Figure 2)
Package Power Dissipation
(14 Lead PIDP)
@ T
A
≤ +25˚C
(16 Lead SOIC)
@ T
A
≥ +25°C
(14 Lead PDIP)
(14 Lead PDIP)
Thermal Resistance, Junction to
Ambient
(14 Lead PDIP)
(16 Lead SOIC)
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
-0.3
V
CC
- 25
V
SS
- 0.3
—
—
—
—
—
—
-55
—
Max.
1225
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+ 0.3
V
SS
+ 25
V
CC
+ 0.3
V
DD
+ 0.3
50
1.6
1.25
75
100
125
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The Input / Output logic timing diagram is shown in Figure 1. For proper operation the device should be used
within the recommended conditions. The V
S
and V
SS
offset ratings are tested with all supplies biased at 15 V
differential.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
†
††
Definition
High Side Floating Supply Absolute Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
Min.
V
S
+ 12
†
V
S
12
0
V
SS
+ 3
††
-5
V
SS
Max.
V
S
+ 20
1200
V
B
20
V
CC
V
SS
+ 20
5
V
DD
Units
V
Logic operational for V
S
of -5 to +1200V. Logic state held for V
S
of -5V to -V
BS
. (Please refer to the Design Tip DT97-
3 for more details).
When V
DD
<5V, the minimum V
SS
offset is limited to -V
DD
3
www.irf.com
© 2014 International Rectifier
February 4, 2014
IR2213(S)PBF
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15 V, C
L
= 1000 pF, T
A
= 25 °C and V
SS
= COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in Figure 3.
Symbol
t
on
t
off
t
sd
t
r
t
f
MT
Definition
Turn-On Propagation Delay
Turn-Off Propagation Delay
Shutdown Propagation Delay
Turn-On Rise Time
Turn-Off Fall Time
Delay Matching, HS & LS Turn-
On/Off
Min.
—
—
—
—
—
—
Typ.
280
225
230
25
17
—
Max.
—
—
—
—
—
30
ns
Units
Test Conditions
V
S
= 0V
V
S
= 1200V
V
S
= 1200V
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15 V, T
A
= 25 °C and V
SS
= COM unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to V
SS
and are applicable to all three logic input leads: HIN, LIN and SD. The V
O
and
I
O
parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
QDD
I
IN+
I
IN-
V
BSUV+
V
BSUV-
V
CCUV+
V
CCUV-
I
O+
I
O-
Definition
Logic ―1‖ Input Voltage
Logic ―0‖ Input Voltage
High Level Output Voltage, V
BIAS
- V
O
Low Level Output Voltage, V
O
Offset Supply Leakage Current
Quiescent V
BS
Supply Current
Quiescent V
CC
Supply Current
Quiescent V
DD
Supply Current
Logic ―1‖ Input Bias Current
Logic ―0‖ Input Bias Current
V
BS
Supply Undervoltage Positive
Going Threshold
V
BS
Supply Undervoltage Negative
Going Threshold
V
CC
Supply Undervoltage Positive
Going Threshold
V
CC
Supply Undervoltage Negative
Going Threshold
Output High Short Circuit Pulsed
Current
Output Low Short Circuit Pulsed
Current
Min.
9.5
—
—
—
—
—
—
—
—
—
8.7
7.9
8.7
7.9
1.7
2.0
Typ.
—
—
—
—
—
125
180
15
20
—
10.2
9.3
10.2
9.3
2.0
2.5
Max.
—
6.0
1.2
0.1
50
230
340
30
40
1.0
11.7
10.7
11.7
10.7
—
—
V
O
= 0V, V
IN
= V
DD
PW ≤ 10 µs
V
O
= 15V, V
IN
= 0V
PW ≤ 10 µs
V
Units
Test Conditions
V
µA
I
O
= 0A
I
O
= 0A
V
B
= V
S
= 1200V
V
IN
= 0V or V
DD
V
IN
= 0V or V
DD
V
IN
= 0V or V
DD
V
IN
= V
DD
V
IN
= 0V
A
4
www.irf.com
© 2014 International Rectifier
February 4, 2014
IR2213(S)PBF
Functional Block Diagram
5
www.irf.com
© 2014 International Rectifier
February 4, 2014
京公网安备 11010802033920号
EEWORLD
