Data Sheet No. PD60201 Rev.D
IR2301(S) & (PbF)
HIGH AND LOW SIDE DRIVER
Features
•
Floating channel designed for bootstrap operation
•
•
•
•
•
•
•
•
Fully operational to +600V
Tolerant to negative transient voltage dV/dt immune
Gate drive supply range from 5 to 20V
Undervoltage lockout for both channels
3.3V, 5V and 15V input logic compatible
Matched propagation delay for both channels
Logic and power ground +/- 5V offset.
Lower di/dt gate driver for better noise immunity
Outputs in phase with inputs
Also available LEAD-FREE (PbF)
Packages
8 Lead PDIP
IR2301
8 Lead SOIC
IR2301S
Description
2106/2301//2108//2109/2302/2304 Feature Comparison
The IR2301(S) are high voltage, high speed
Cross-
Input
conduction
power MOSFET and IGBT drivers with indepen-
Dead-Time
Ground Pins
Part
prevention
logic
dent high and low side referenced output
logic
2106/2301
channels. Proprietary HVIC and latch immune
COM
HIN/LIN
no
none
21064
VSS/COM
CMOS technologies enable ruggedized mono-
2108
Internal 540ns
COM
HIN/LIN
yes
lithic construction. The logic input is compatible
Programmable 0.54~5
µs
21084
VSS/COM
with standard CMOS or LSTTL output, down to
2109/2302
Internal 540ns
COM
IN/SD
yes
3.3V logic. The output drivers feature a high
Programmable 0.54~5
µs
21094
VSS/COM
pulse current buffer stage designed for minimum
yes
Internal 100ns
HIN/LIN
COM
2304
driver cross-conduction. The floating channel
can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to
600 volts.
Typical Connection
up to 600V
(Refer to Lead
Assignments for
correct pin con-
figuration). This/
T h e s e
diagram(s)
show electrical
connections
only. Please re-
fer to our Appli-
cation Notes
and DesignTips
for proper circuit
board layout.
V
CC
V
CC
HIN
LIN
V
B
HO
V
S
LO
TO
LOAD
HIN
LIN
COM
IR2301
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1
IR2301(S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
dV
S
/dt
P
D
Rth
JA
T
J
T
S
T
L
Definition
High side floating absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage
Allowable offset supply voltage transient
Package power dissipation @ T
A
≤
+25°C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
(8 lead PDIP)
(8 lead SOIC)
(8 lead PDIP)
(8 lead SOIC)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
COM - 0.3
—
—
—
—
—
—
-50
—
Max.
625
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+ 0.3
V
CC
+ 0.3
50
1.0
0.625
125
200
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The V
S
offset rating is tested with all supplies biased at 15V differential.
Symbol
VB
V
S
V
HO
V
CC
V
LO
V
IN
T
A
Definition
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage
Ambient temperature
Min.
V
S
+ 5
Note 1
V
S
5
0
COM
-40
Max.
V
S
+ 20
600
V
B
20
V
CC
V
CC
150
Units
V
°
C
Note 1: Logic operational for V
S
of -5 to +600V. Logic state held for V
S
of -5V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
2
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IR2301(S) & (PbF)
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, C
L
= 1000 pF, T
A
= 25°C.
Symbol
ton
toff
MT
tr
tf
Definition
Turn-on propagation delay
Turn-off propagation delay
Delay matching, HS & LS turn-on/off
Turn-on rise time
Turn-off fall time
Min.
—
—
—
—
—
Typ.
220
200
0
130
50
Max. Units Test Conditions
300
280
50
220
80
nsec
V
S
= 0V
V
S
= 0V
V
S
= 0V
V
S
= 0V or 600V
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, and T
A
= 25°C unless otherwise specified. The V
IL
, V
IH
and I
IN
parameters are referenced to
COM and are applicable to the respective input leads. The V
O
, I
O
and Ron parameters are referenced to COM and are
applicable to the respective output leads: HO and LO.
Symbol
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
CCUV+
V
BSUV+
V
CCUV-
V
BSUV-
V
CCUVH
V
BSUVH
I
O+
I
O-
Definition
Logic “1” input voltage
Logic “0” input voltage
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Logic “1” input bias current
Logic “0” input bias current
V
CC
and V
BS
supply undervoltage positive
going threshold
V
CC
and V
BS
supply undervoltage negative
negative going threshold
Hysteresis
Output high short circuit pulsed current
Output low short circuit pulsed current
Min. Typ. Max. Units Test Conditions
2.9
—
—
—
—
20
50
—
—
3.3
3
0.1
120
250
—
—
0.8
0.3
—
60
120
5
—
4.1
3.8
0.3
200
350
—
0.8
1.4
0.6
50
100
190
20
2
5
4.7
—
—
—
mA
V
O
= 0V,
PW
≤
10
µs
V
O
= 15V,
PW
≤
10
µs
µA
V
V
CC
= 10V to 20V
V
CC
= 10V to 20V
I
O
= 20 mA
I
O
= 20 mA
V
B
= V
S
= 600V
V
IN
= 0V or 5V
V
IN
= 0V or 5V
V
IN
= 5V
V
IN
= 0V
V
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3
IR2301(S) & (PbF)
Functional Block Diagrams
VB
UV
DETECT
R
HV
LEVEL
SHIFTER
PULSE
GENERATOR
PULSE
FILTER
R
S
Q
HO
HIN
VSS/COM
LEVEL
SHIFT
VS
VCC
UV
DETECT
LO
LIN
VSS/COM
LEVEL
SHIFT
DELAY
COM
Lead Definitions
Symbol Description
HIN
LIN
V
B
HO
V
S
V
CC
LO
COM
Logic input for high side gate driver output (HO), in phase
Logic input for low side gate driver output (LO), in phase
High side floating supply
High side gate drive output
High side floating supply return
Low side and logic fixed supply
Low side gate drive output
Low side return
4
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IR2301(S) & (PbF)
Lead Assignments
1
2
3
4
VCC
HIN
LIN
COM
VB
HO
VS
LO
8
7
6
5
1
2
3
4
VCC
HIN
LIN
COM
VB
HO
VS
LO
8
7
6
5
8 Lead PDIP
8 Lead SOIC
IR2301
IR2301S
HIN
LIN
HIN
LIN
ton
50%
50%
tr
90%
toff
90%
tf
HO
LO
Figure 1. Input/Output Timing Diagram
HO
LO
10%
10%
Figure 2. Switching Time Waveform Definitions
HIN
LIN
50%
50%
LO
HO
10%
MT
90%
MT
LO
HO
Figure 3. Delay Matching Waveform Definitions
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