SL74HCT153
Dual 4-Input Data Selector/Multiplexer
High-Performance Silicon-Gate CMOS
The SL74HCT153 is identical in pinout to the LS/ALS153. The
SL74HCT153 may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
The Address Inputs select one of four Data Inputs from each
multiplexer. Each multiplexer has an active-low Strobe control and a
noninverting output.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0
µA
O
RDERING INFORMATION
SL74HCT153N Plastic
SL74HCT153D SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
A1
X
L
PIN 16 =V
CC
PIN 8 = GND
L
H
H
A0
X
L
H
L
H
Strobe
H
L
L
L
L
Output
Y
L
D0
D1
D2
D3
D0,D1...D3=the level of the respective
Data Input
X = don’t care
SLS
System Logic
Semiconductor
SL74HCT153
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min
4.5
0
-55
0
Max
5.5
V
CC
+125
500
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HCT153
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
2.0
2.0
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
4.0
≤85
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
40
≤125
°C
2.0
2.0
0.8
0.8
4.4
5.4
3.7
0.1
0.1
0.4
±1.0
160
µA
µA
V
Unit
V
IH
V
IL
V
OH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
4.0 mA
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
V
V
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
4.0 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
Additional Quiescent
Supply Current
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
V
IN
= 2.4 V, Any One Input
V
IN
=V
CC
or GND, Other
Inputs
I
OUT
=0µA
∆I
CC
≥-55°C
25°C to
125°C
2.4
mA
5.5
2.9
SLS
System Logic
Semiconductor
SL74HCT153
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
TLH
, t
THL
C
IN
Parameter
Maximum Propagation Delay, Input D to
Output Y (Figures 1 and 4)
Maximum Propagation Delay , Input A to
Output Y (Figures 2 and 4)
Maximum Propagation Delay , Strobe to
Output Y (Figures 3 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Muliplexer)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
25
°C
to
-55°C
34
34
27
15
10
≤85°C
43
43
34
19
10
≤125°C
51
51
41
22
10
Unit
ns
ns
ns
ns
pF
Typical @25°C,V
CC
=5.0 V
40
pF
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
SLS
System Logic
Semiconductor
SL74HCT153
EXPANDED LOGIC DIAGRAM
SLS
System Logic
Semiconductor
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