P1707A
Notebook LCD Panel EMI
Reduction IC
Description
The P1707A is a versatile spread spectrum frequency modulator
designed specifically for input clock frequencies. The P1707A
reduces electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of down stream clock and data
dependent signals. The P1707A allows significant system cost savings
by reducing the number of circuit board layers, ferrite beads,
shielding, and other passive components that are traditionally required
to pass EMI regulations.
The P1707A modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, and more importantly,
decreases the peak amplitudes of its harmonics. This results in
significantly lower system EMI compared to the typical narrow band
signal produced by oscillators and most frequency generators.
Lowering EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation.’
The P1707A uses the most efficient and optimized modulation
profile approved by the FCC and is implemented in a proprietary all
digital method.
Applications
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SOIC−8
S SUFFIX
CASE 751BD
TSSOP−8
T SUFFIX
CASE 948AL
PIN CONFIGURATION
CLKIN
VDD
VSS
ModOUT
(Top View)
1
NC
SR0
SR1
SSON/SBM
The P1707A is targeted towards notebook LCD displays, and other
displays using an LVDS interface, PC peripheral devices, and
embedded systems.
Features
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
•
FCC Approved Method of EMI Attenuation
•
Generates a Low EMI Spread Spectrum Clock of the Input
•
•
•
•
•
•
•
•
•
•
•
Frequency
Optimized for Frequency Range from 40 MHz to 175 MHz
Internal Loop Filter Minimizes External Components and Board
Space
Four Selectable Spread Ranges
Low Inherent Cycle−to−Cycle Jitter
3.3 V Operating Voltage
Ultra−low Power CMOS Design
−
14.85 mA @ 3.3 V, 140 MHz
−
16.69 mA @ 3.3 V, 162 MHz
−
17.78 mA @ 3.3 V, 175 MHz
Supports Notebook VGA and Other LCD Timing Controller
Applications
Pinout Compatible to ICS MK1707 and Cypress CY25561 /
CY25560
SSON / SBM Pin for Spread Spectrum On/Off and Standby Mode
Controls
Available in 8−pin SOIC and TSSOP Packages
These are Pb−Free Devices
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. 3
1
Publication Order Number:
P1707A/D
P1707A
SR0 SR1 SSON / SBM
VDD
PLL
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin#
1
Pin Name
CLKIN
Type
I
VSS
Description
Connect to externally generated clock signal. To put the part into standby mode, disable
the input clock signal to this pin and pull SSON/SBM (pin 5) low. Refer to
Standby Mode
Selection
Table.
Connect to +3.3 V. (Place a decoupling 0.1
mF
close to pin and ground.)
Ground Connection. Connect to system ground.
Spread spectrum clock output.
Spread Spectrum On/Off and standby mode control. Refer to
Standby Mode Selection
Table. This pin has an internal pull−up resistor.
Digital logic input used to select Spreading Range. Refer to
Spread Spectrum Selection
Table. This pin has an internal pull−up resistor.
Digital logic input used to select Spreading Range. Refer to
Spread Spectrum Selection
Table. This pin has an internal pull−up resistor.
No connect.
2
3
4
5
6
7
8
VDD
VSS
ModOUT
SSON / SBM
SR1
SR0
NC
P
P
O
I
I
I
−
Table 2. STANDBY MODE SELECTION
CLKIN
Disabled
Disabled
Enabled
Enabled
SSON / SBM
0
1
0
1
Spread Spectrum
N/A
N/A
Off
On
ModOUT
Disabled
Disabled
Reference
Normal
PLL
Disabled
Free Running
Disabled
Normal
Mode
Standby
Free Running
Buffer out
Normal
Table 3. SPREAD RANGE SELECTION
SR1
0
0
1
1
SR0
0
1
0
1
Spreading Range
±1.50%
±2.50%
±0.50%
±1.00%
Modulation Rate
(F
IN
/80) * 34.72 KHz
(F
IN
/80) * 34.72 KHz
(F
IN
/80) * 34.72 KHz
(F
IN
/80) * 34.72 KHz
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2
P1707A
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD, V
IN
T
STG
T
A
T
s
T
J
T
DV
Parameter
Voltage on any pin with respect to Ground
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Rating
−0.5
to +4.6
−65
to +125
−40
to +85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. DC ELECTRICAL CHARACTERISTICS
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
CC
I
DD
VDD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
(pull−up resistors on inputs SR0, SR1 and SSON / SBM)
Input high current
X
OUT
output low current (V
XOL
@ 0.4 V, VDD = 3.3 V)
X
OUT
output high current (V
XOH
@ 2.5 V, VDD = 3.3 V)
Output low voltage VDD = 3.3 V, I
OL
= 20 mA
Output high voltage VDD = 3.3 V, I
OH
= 20 mA
Dynamic supply current normal mode
3.3 V and 10 pF loading
Static supply current standby mode
Operating voltage
Power up time (first locked clock cycle after power up)
Clock output impedance
2.7
2.5
8.46
12
0.6
3.3
0.18
20
3.7
17.78
3
3
0.4
Parameter
Min
VSS−0.3
2.0
Typ
Max
0.8
VDD+0.3
−35
35
Unit
V
V
mA
mA
mA
mA
V
V
mA
mA
V
mS
W
Table 6. AC ELECTRICAL CHARACTERISTICS
Symbol
f
IN
f
OUT
t
LH
(Note 1)
t
HL
(Note 1)
t
JC
t
D
Input frequency
Output frequency
Output rise time (Measured from 0.8 V to 2.0 V)
Output fall time (Measured from 2.0 V to 0.8 V)
Jitter (Cycle−to−cycle)
Output duty cycle
Parameter
Min
40
40
0.7
0.6
−
45
0.9
0.8
−
50
Typ
Max
175
175
1.1
1.0
360
55
Unit
MHz
MHz
nS
nS
pS
%
1. t
LH
and t
HL
are measured into a capacitive load of 15 pF.
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