Philips Semiconductors
Preliminary specification
Pager receiver
FEATURES
•
Double frequency conversion, zero-IF receiver with:
– Configurable in all paging bands (130 to 930 MHz)
– Low noise amplifier featured with four step Automatic
Gain Control (AGC)
– Down-conversion mixers
– On-chip, zero-IF channel filter
– I/Q, non-demodulated outputs
– Highpass filters to remove DC offsets.
•
External Voltage Controlled Oscillator (VCO):
– Both Local Oscillators (LOs) derived from the VCO.
APPLICATIONS
•
FLEX
TM
, ERMES and POCSAG pagers
•
Remote control terminals.
GENERAL DESCRIPTION
The UAA3500HL is a one-chip pager receiver complying
with POCSAG, FLEX
TM
and ERMES standards. The IC
performs in accordance with specifications in the
−10
to +55
°C
temperature range.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
UAA3500HL
LQFP48
DESCRIPTION
UAA3500HL
The UAA3500HL contains a front-end receiver, which can
be configured through external components for any
frequency band between 130 and 930 MHz. The back-end
receiver consists of the channel filter and limiters. An
external VCO ensures the Local Oscillator (LO) for the
front-end. Designed in an advanced BiCMOS process, it
combines high performance with low-power consumption
and a high degree of integration, thus reducing external
component costs and total radio size.
Its first advantage is to remove the expensive SAW filter
necessary in a superhet architecture, replacing it by an
integrated, elliptic channel filter that provides 70 dB
adjacent channel rejection. The receive front-end section
consists of a low-noise amplifier that drives mixers through
an external LC image rejection filter. The output drives the
I and Q second mixers, whose outputs are at zero
frequency. The receiver back-end section consists of
filters (channel filtering), limiters (limited output required)
and high-pass filters (DC block) to remove DC offsets.
Outputs are I and Q, undemodulated signals.
Its second advantage is to provide the two LO signals from
one VCO only, tuned by a PLL. An on-chip frequency
divider-by-2 and buffers provide the LO sources.
Its third advantage is to provide two voltage regulators,
allowing to obtain 1.0 and 1.8 V regulated voltages.
VERSION
SOT313-2
plastic low profile quad flat package; 48 leads; body 7
×
7
×
1.4 mm
2000 Jan 18
2
Philips Semiconductors
Preliminary specification
Pager receiver
QUICK REFERENCE DATA
SYMBOL
V
CC1
V
CC2
I
CC1(RX)
PARAMETER
supply voltage 1
(B++;see note 2)
supply voltage 2
(B+; see note 2)
supply current from B++
RX section on; DC tested
f
RF
= 160 MHz
f
RF
= 280 MHz
f
RF
= 930 MHz
I
CC2(RX)
supply current from B+
RX section on; DC tested
f
RF
= 160 MHz
f
RF
= 280 MHz
f
RF
= 930 MHz
NF
RX
receiver noise figure
from RF input to 2nd mixer input
f
RF
= 160 MHz
f
RF
= 280 MHz
f
RF
= 930 MHz
P
i(ref)
RF input sensitivity
3% BER
f
RF
= 160 MHz; 1600 bits/s 2-level FSK
f
RF
= 280 MHz; 1600 bits/s 2-level FSK
f
RF
= 930 MHz; 6400 bits/s 2-level FSK
f
RF
= 930 MHz; 6400 bits/s 4-level FSK
ACR
T
amb
Notes
adjacent channel rejection
ambient temperature
−
−
−
−
65
−10
−
−
−
−
−
1.85
−
−
2.35
CONDITIONS
(1)
MIN.
1.85
1.05
UAA3500HL
TYP.
2.1
1.4
MAX. UNIT
3.3
1.5
V
V
2.4
2.4
2.7
1.3
1.4
2.3
2.7
3.1
4.4
−128.5
−128
−126.5
−123
70
+25
−
−
3
−
−
2.45
−
−
−
−
−
−
−
−
+55
mA
mA
mA
mA
mA
mA
dB
dB
dB
dBm
dBm
dBm
dBm
dB
°C
1. For 930 MHz band; for other conditions see Chapters “DC characteristics” and “AC characteristics”.
2. For B+ and B++, see Fig.3.
2000 Jan 18
3
Philips Semiconductors
Preliminary specification
Pager receiver
PINNING
SYMBOL
CAPI3B
CAPI3A
CAPI2A
CAPI2B
V
CC(O)
OUTI
OUTQ
OGND
CAPQ2B
CAPQ2A
CAPQ3A
CAPQ3B
GYRCO2
GYRCO1
GYROUTQ
DRV1
V
CC(FE)
V
CC(DC)
CAPQ1B
CAPQ1A
LOIN
LOGND
FASTON
V
CC(LO)
DRV2
AGCADJ
AGCTAU
RXON
LNAGND1
RFINB
RFINA
LNAGND2
RSET
RSSI
IMINA
IMINB
M1GND
IMOUTA
IMOUTB
M2GND
2000 Jan 18
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DESCRIPTION
3rd DC filter (I path) external capacitor B (I path)
3rd DC filter (I path) external capacitor A (I path)
2nd DC filter (I path) external capacitor A (I path)
2nd DC filter (I path) external capacitor A (I path)
output stage supply voltage B++ (I path)
output I and Q signals (I path)
output I and Q signals (Q path)
output stage ground
2nd DC filter external capacitor B (Q path)
2nd DC filter external capacitor A (Q path)
3rd DC filter external capacitor A (Q path)
3rd DC filter external capacitor B (Q path)
external resistor to set-up gyrator filter cut-off frequency
external resistor to set-up gyrator filter cut-off frequency
Q-gyrator output
regulator driver (1.8 V)
regulated voltage for front-end (1.8 V)
input voltage from DC-to-DC converter (2.1 V)
1st DC filter external capacitor (Q path)
1st DC filter external capacitor (Q path)
LO input
LO strip ground
fast mode enable
regulated voltage for LO strip (1.0 V)
regulator driver (1.0)
AGC loop gain control
AGC loop time constant
receiver mode enable
receiver LNA (Low Noise Amplifier) ground 1
LNA input B
LNA input A
receiver LNA ground 2
LNA current setup
received signal strength indicator
image rejection filter input A
image rejection filter input B
first mixer ground
image rejection filter output A
image rejection filter output B
second mixers ground
5
UAA3500HL
京公网安备 11010802033920号
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