SCG2001G-N8
Jitter Filter
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Application
The Connor-Winfield SCG2001G-N8
provides high precision phase lock loop
frequency translation for
telecommunication applications.
SCG2001G-N8 accepts an 8.192 MHz
CMOS reference signal and provides a low
phase gain, jitter filtered, wander following
8.192 MHz CMOS output.
This product is RoHS compliant.
Features
•
3.3V High
Precision PLL
•
Tri-State Capability
•
Active Alarms
•
Guaranteed Free
Run ±20ppm
•
1 Sec. Acquisition
Time
•
RoHS Compliant
•
<15 Hz Bandwidth
Bulletin
Page
Revision
Date
Issued By
SG151
1 of 14
P01
10 MAY 07
ENG
General Description
The SCG2001G-N8 provides high precision phase lock loop
frequency translation for the telecommunication applications.
The SCG2001G-N8 products generate a CMOS output from an
intrinsically low jitter, voltage controlled crystal oscillator.
SCG2001G-N8 is well suited for use in line cards, service
termination cards and similar functions to provide reliable
reference, phase locked, synchronization for TDM, PDH, SONET
and SDH network equipment . The SCG2001G-N8 provides a
low phase gain (<0.2dB), jitter filtered, wander following output
signal synchronized to a superior Stratum or peer input reference
signal.
The SCG2001G-N8 include the following features: Free Run,
Tri-state and alarm outputs for Loss-of-Reference, (LOR), Loss-
of-Lock, (LOL). During the LOR alarm, the SCG2001G-N8 will
also enter a Free Run state which will guarantee a 20 ppm
accurate output. Additionally the Free Run mode may be
entered manually by asserting a high signal to the Free
Run Enable pin. The outputs, except the oscillator output,
may be put into the tri-state high impedance condition for
external testing purposes by asserting a high signal to the
Tri-State Enable pin.
The SCG2001G-N8 are 3.3 Volt components that
typically draw less than 70 mA. The SCG2001G-N8 has
an acquisition time of approximately 1.0 second and can
be used in applications that require temperature rating of
0° - 70° C. The SCG2001G-N8 has a 33Ω resistor in
series with the oscillator output. The SCG2001G-N8
maximum package dimensions are .78” x .83” x .35” on a
six layer FR4 board with surface mount pins. Parts are
assembled using high temperature solder to withstand
surface mount reflow process.
Pin Description
Table 1
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Connection
-
TCK
TMS
Ground
Free Run Enable/TDI
Loss of Reference (LOR)
Loss of Lock (LOL)
Reference Input
Oscillator Output
Tri-State enable
Vcc
TDO
-
-
Description
Not Used
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
Ground
Free Run enable pin. 1 = Free Run at nominal frequency ±20ppm. Input is internally
pulled to GND
Alarm indicator. 1 = The reference has been lost.
Alarm indicator. 1 = Phase lock has been lost
Input reference frequency
Output frequency is dependent on SCG model
Tri State control for all outputs except Oscillator Output. 1 = Hi-Z, 0 = normal.
Input is internally pulled to GND.
3.3V Supply Voltage.
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
Not Used
Not Used
Absolute Maximum Rating
Table 2
Symbol
Vcc
V1
Ts
Parameter
Power Supply Voltage
Input Voltage
Storage Temperature
Minimum
-0.5
-0.5
-65
Nominal
Maximum
4
5.5
150
Units
Volts
Volts
deg. C
Notes
Data Sheet #:
SG151
Page
2
of
14
Rev:
P01
Date:
5/10/07
© Copyright 2007 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Specifications
Table 3
Parameter
Voltage
Current
Temperature Range
Output Frequency
Input Frequency
Input Jitter Tolerance
(Input Jitter Frequencies > 10 Hz)
Specifications
3.3V ±5%
56 mA Typical
0 to 70°C
8.192 MHz
8.192 MHz
>1
us Typical
<15 Hz
Approx 1.0 second
±50 ppm Minimum
45/55 % Min/Max @ 50% Level
5 ns @ 20% to 80% output level
15 pF
LOR, LOL Status on seperate outputs
±20 ppm
Fr4 SM 0.78" x .83" x 0.35" (maximum)
60 ps Typical
750 ps Typical
± 26 ns Maximum
± 20 ns Maximum
Notes
1.0
Jitter Bandwidth
Acquisition Time
Capture/Pull-in Range
Output Duty Cycle
Output Rise and Fall Time
Output Load
Alarms
Free Run Accuracy
Package
TDEV
MTIE
Static Offset
Dynamic Offset
2.0
Reference Output/Oscillator Output Offset
≤
8 ns
3.0
4.0
Input And Output Characteristics
Table 4
Symbol
V
IH
V
IL
T
IO
C
O
V
HO
V
IO
T
IR
Parameter
High Level Input Voltage
Low Level Input Voltage
I/O to Output Valid
Output Capacitance
High Level Output Voltage l
oH
= -4mA
Low Level Output Voltage l
oL
= 8mA
Input Reference Signal Pulse Width
30
2.4
0.4
nS
Minimum
2
0
Nominal
Maximum
5.5
0.8
10
10
Units
V
V
nS
pF
Vcc Min.
Vcc Max.
Notes
Output Jitter Specifications
Table 5
Jitter BW 10 Hz - 20 MHz
Frequency (MHz)
8.192
NOTES:
`
1.0:
2.0:
3.0:
4.0:
SONET Jitter BW 12 KHz - 20 MHz
pS (RMS)
3 Typ.
m UI
0.025 Typ.
pS (RMS)
30 Typ.
m UI
0.246 Typ.
Requires external regulation
From a 20 ppm offset in reference frequency
Offset between Reference Input and Reference Output @ room temp.
Offset change between Reference Input and Reference Output over temperature range from room temperature.
Data Sheet #:
SG151
Page
3
of
14
Rev:
P01
Date:
5/10/07
© Copyright 2007 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Embedded System
京公网安备 11010802033920号
EEWORLD
