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ZVP3310A_15

Description
P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET
File Size134KB,4 Pages
ManufacturerDiodes
Websitehttp://www.diodes.com/
Download Datasheet View All

ZVP3310A_15 Overview

P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

P-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 100 Volt V
DS
* R
DS(on)
=20Ω
ZVP3310A
D
G
S
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at T
amb
=25°C
Pulsed Drain Current
Gate Source Voltage
Power Dissipation at T
amb
=25°C
Operating and Storage Temperature Range
SYMBOL
V
DS
I
D
I
DM
V
GS
P
tot
T
j
:T
stg
E-Line
TO92 Compatible
VALUE
-100
-140
-1.2
±
20
UNIT
V
mA
A
V
mW
°C
625
-55 to +150
ELECTRICAL CHARACTERISTICS (at T
amb
= 25°C unless otherwise stated).
PARAMETER
Drain-Source Breakdown
Voltage
Gate-Source Threshold
Voltage
Gate-Body Leakage
Zero Gate Voltage Drain
Current
On-State Drain Current(1)
SYMBOL MIN.
BV
DSS
V
GS(th)
I
GSS
I
DSS
I
D(on)
-300
20
50
50
15
5
8
8
8
8
-100
-1.5
-3.5
20
-1
-50
MAX. UNIT CONDITIONS.
V
V
nA
µ
A
µ
A
I
D
=-1mA, V
GS
=0V
ID=-1mA, V
DS
= V
GS
V
GS
=
±
20V, V
DS
=0V
V
DS
=-100V, V
GS
=0
V
DS
=-80V, V
GS
=0V, T=125°C
(2)
V
DS
=-25 V, V
GS
=-10V
V
GS
=-10V,I
D
=-150mA
V
DS
=-25V,I
D
=-150mA
mA
Static Drain-Source On-State R
DS(on)
Resistance (1)
Forward Transconductance
(1)(2)
Input Capacitance (2)
Common Source Output
Capacitance (2)
Reverse Transfer
Capacitance (2)
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
mS
pF
pF
pF
ns
ns
ns
ns
V
DS
=-25V, V
GS
=0V, f=1MHz
V
DD
-25V, I
D
=-150mA
(1) Measured under pulsed conditions. Width=300
µ
s. Duty cycle
2%
(2) Sample test.
3-432
Switching times measured with 50
source impedance and <5ns rise time on a pulse generator
(
3
)
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