IDT71V35761166PF datasheet, PDF

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IDT71V35761166PF: DescriptionCache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100; Categorystorage storage; File Size520KB，23 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT71V35761166PF Overview

Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100

IDT71V35761166PF Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Objectid	1989610846
Parts packaging code	QFP
package instruction	LQFP, QFP100,.63X.87
Contacts	100
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	3.5 ns
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	4718592 bit
Memory IC Type	CACHE SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.03 A
Minimum standby current	3.14 V
Maximum slew rate	0.32 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm

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128K x 36, 256K x 18

3.3V Synchronous SRAMs

3.3V I/O, Pipelined Outputs

Burst Counter, Single Cycle Deselect

IDT71V35761

IDT71V35781

Features

128K x 36, 256K x 18 memory configurations

Supports high system speed:

Commercial:

– 200MHz 3.1ns clock access time

Commercial and Industrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array

Description

The IDT71V35761/781 are high-speed SRAMs organized as

128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data,

address and control registers. Internal logic allows the SRAM to generate

a self-timed write based upon a decision which can be left until the end of

the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V35761/81 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the

LBO

input pin.

The IDT71V35761/781 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and 165 fine pitch ball grid array.

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

5301 tbl 01

NOTE:

and

are not applicable for the IDT71V35781.

OCTOBER 2000

DSC-5301/01

IDT71V35761166PF Related Products

	IDT71V35761166PF	71V35781200BQ	IDT71V35781200BQ	71V35761166PF
Description	Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100	Cache SRAM, 256KX18, 3.1ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	Standard SRAM, 256KX18, 3.1ns, CMOS, PBGA165	Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP-100
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant
Maximum access time	3.5 ns	3.1 ns	3.1 ns	3.5 ns
Maximum clock frequency (fCLK)	166 MHz	200 MHz	200 MHz	166 MHz
I/O type	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PQFP-G100	R-PBGA-B165	R-PBGA-B165	R-PQFP-G100
JESD-609 code	e0	e0	e0	e0
memory density	4718592 bit	4718592 bit	4718592 bit	4718592 bit
Memory IC Type	CACHE SRAM	CACHE SRAM	STANDARD SRAM	CACHE SRAM
memory width	36	18	18	36
Humidity sensitivity level	3	3	3	3
Number of terminals	100	165	165	100
word count	131072 words	262144 words	262144 words	131072 words
character code	128000	256000	256000	128000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	128KX36	256KX18	256KX18	128KX36
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	TBGA	BGA	LQFP
Encapsulate equivalent code	QFP100,.63X.87	BGA165,11X15,40	BGA165,11X15,40	QFP100,.63X.87
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	GRID ARRAY, THIN PROFILE	GRID ARRAY	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	240	225	225	240
power supply	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum standby current	0.03 A	0.03 A	0.03 A	0.03 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	0.32 mA	0.36 mA	0.36 mA	0.32 mA
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	BALL	BALL	GULL WING
Terminal pitch	0.65 mm	1 mm	1 mm	0.65 mm
Terminal location	QUAD	BOTTOM	BOTTOM	QUAD
Maximum time at peak reflow temperature	20	20	20	20
package instruction	LQFP, QFP100,.63X.87	13 X 15 MM, FBGA-165	-	LQFP, QFP100,.63X.87
length	20 mm	15 mm	-	20 mm
Number of functions	1	1	-	1
Maximum seat height	1.6 mm	1.2 mm	-	1.6 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V	-	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	-	3.135 V
width	14 mm	13 mm	-	14 mm

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