M74HC4060
14-stage binary counter/oscillator
Datasheet
-
production data
Applications
Automotive
Industrial
Computer
Consumer
Description
Features
High speed:
f
max
= 65 MHz (typ.) at V
CC
= 6 V
Low power dissipation:
I
CC
= 4 A (max.) at T
A
= 25 °C
High noise immunity:
V
NIH
= V
NIL
= 28% V
CC
(min.)
Symmetrical output impedance:
|I
OH
| = I
OL
= 4 mA (min.)
Balanced propagation delays: T
PLH
T
PHL
Wide operating voltage range:
V
CC
(opr.) = 2 V to 6 V
Pin and function compatible with 74 series
4060
The M74HC4060 device is a high speed CMOS
14-stage binary counter/oscillator fabricated with
silicon gate C
2
MOS technology.
The oscillator configuration allows design of either
RC or crystal oscillator circuits. A high level on the
CLEAR accomplishes the reset function, i.e. all
counter outputs are made low and the oscillator is
disabled.
A negative transition on the clock input
increments the counter. Ten kinds of divided
output are provided; 4 to 10 and 12 to 14 stage
inclusive. The maximum division available at Q12
is 1/16384 of the oscillator frequency.
The
I
input and the CLEAR input are equipped
with protection circuits against static discharge
and transient excess voltage.
Table 1. Device summary
Ordering code
M74HC4060B1R
M74HC4060RM13TR
M74HC4060YRM13TR
(1)
M74HC4060TTR
M74HC4060YTTR
(1)
Temperature range
-55 °C to +125 °C
-55 °C to +125 °C
-40 °C to +125 °C
-55 °C to +125 °C
-40 °C to +125 °C
Package
PDIP-16
SO-16
SO-16 (automotive version)
TSSOP-16
TSSOP-16 (automotive version)
Marking
M74HC4060B1
74HC4060
74HC4060Y
HC4060
HC4060Y
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC
Q001 and Q002 or equivalent.
May 2013
This is information on a product in full production.
DocID1967 Rev 2
1/16
www.st.com
16
Contents
M74HC4060
Contents
1
2
3
4
5
6
7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
DocID1967 Rev 2
M74HC4060
Pin description
1
Pin description
Figure 1. Pin connection and IEC logic symbols
Figure 2. Input and output equivalent circuit
Table 2. Pin description
Pin no
1, 2, 3
7, 5, 4, 6, 14, 13, 15
9
10
11
12
8
16
Symbol
Q12 to Q14
Q4 to Q10
O
O
I
CLEAR
GND
V
CC
Name and function
Counter outputs
Counter outputs
External capacitor connection
External resistor connection
Clock input / oscillator pin
Master reset
Ground (0 V)
Positive supply voltage
DocID1967 Rev 2
3/16
M74HC4060
Maximum ratings
3
Maximum ratings
Table 4. Absolute maximum ratings
(1)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
D
T
stg
T
L
Supply voltage
DC Input voltage
DC output voltage
DC input diode current
DC output diode current
DC output current
DC VCC or ground current
Power dissipation
Storage temperature
Lead temperature (10 sec.)
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
20
20
25
50
500
(2)
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
mW
°C
°C
1. Absolute maximum ratings are those values beyond which damage to the device may occur. Functional
operation under these conditions is not implied.
2. 500 mW at 65 °C; derate to 300 mW by 10 mW/ C from 65 °C to 85 °C.
Table 5. Recommended operating conditions
Symbol
V
C
V
I
V
O
T
op
t
r
, t
f
Parameter
Supply voltage
Input voltage
Output voltage
Operating temperature
V
CC
= 2.0 V
Input rise and fall time
V
CC
= 4.5 V
V
CC
= 6.0 V
Value
2 to 6
0 to V
CC
0 to V
CC
-55 to 125
0 to 1000
0 to 500
0 to 400
Unit
V
V
V
°C
ns
ns
ns
DocID1967 Rev 2
5/16
FPGA/CPLD
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