2.7 V to 5.5 V, 450 μA, Rail-to-Rail Output,
Quad, 12-/16-Bit
nanoDACs
®
AD5624/AD5664
FEATURES
Low power, quad
nanoDACs
AD5664: 16 bits
AD5624: 12 bits
Relative accuracy: ±12 LSBs max
Guaranteed monotonic by design
10-lead MSOP and 3 mm × 3 mm LFCSP_WD
2.7 V to 5.5 V power supply
Power-on reset to zero
Per channel power-down
Serial interface, up to 50 MHz
FUNCTIONAL BLOCK DIAGRAM
V
DD
GND
V
REF
AD5624/AD5664
INPUT
REGISTER
SCLK
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
V
OUT
B
DAC
REGISTER
STRING
DAC A
BUFFER
V
OUT
A
SYNC
INPUT
REGISTER
DIN
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
V
OUT
C
DAC
REGISTER
STRING
DAC D
BUFFER
V
OUT
D
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Figure 1.
Table 1. Related Devices
Part No.
AD5624R/AD5644R/AD5664R
Description
2.7 V to 5.5 V quad, 12-, 14-,
16-bit DACs with internal
reference
GENERAL DESCRIPTION
The AD5624/AD5664, members of the
nanoDAC
family, are
low power, quad, 12-, 16-bit buffered voltage-out DACs that
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design.
The AD5624/AD5664 require an external reference voltage to
set the output range of the DAC. The part incorporates a power-
on reset circuit that ensures the DAC output powers up to 0 V
and remains there until a valid write takes place. The parts
contain a power-down feature that reduces the current
consumption of the device to 480 nA at 5 V and provides
software-selectable output loads while in power-down mode.
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated
equipment. The power consumption is 2.25 mW at 5 V, going
down to 2.4 μW in power-down mode.
The AD5624/AD5664 on-chip precision output amplifier allows
rail-to-rail output swing to be achieved.
The AD5624/AD5664 use a versatile 3-wire serial interface that
operates at clock rates up to 50 MHz, and are compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
Relative accuracy: ±12 LSBs maximum.
Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm,
LFCSP_WD.
Low power, typically consumes 1.32 mW at 3 V and
2.25 mW at 5 V.
Maximum settling time of 4.5 μs (AD5624) and 7 μs
(AD5664).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
05943-001
POWER-ON
RESET
POWER-DOWN
LOGIC
AD5624/AD5664
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 15
D/A Section................................................................................. 15
Resistor String ............................................................................. 15
Output Amplifier........................................................................ 15
Serial Interface ............................................................................ 15
Input Shift Register .................................................................... 16
SYNC Interrupt .......................................................................... 16
Power-On Reset.......................................................................... 16
Software Reset............................................................................. 17
Power-Down Modes .................................................................. 17
LDAC Function .......................................................................... 18
Microprocessor Interfacing....................................................... 19
Applications..................................................................................... 20
Choosing a Reference for the AD5624/AD5664.................... 20
Using a Reference as a Power Supply for the
AD5624/AD5664........................................................................ 20
Bipolar Operation Using the AD5624/AD5664..................... 21
Using AD5624/AD5664 with a Galvanically Isolated
Interface ....................................................................................... 21
Power Supply Bypassing and Grounding................................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
6/06—Revision
0: Initial Version
Rev. 0 | Page 2 of 24
AD5624/AD5664
SPECIFICATIONS
V
DD
= +2.7 V to +5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; V
REF
= V
DD
; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE
2
AD5664
Resolution
Relative Accuracy
Differential Nonlinearity
AD5624
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature
Coefficient
DC Power Supply Rejection
Ratio
DC Crosstalk
2
±1
−0.1
±2
±2.5
−100
10
10
±10
±1
±1.5
Min
A Grade
1
Typ
Max
Min
B Grade
1
Typ
Max
Unit
Conditions/Comments
16
±8
±16
±1
16
±6
±12
±1
Bits
LSB
LSB
Guaranteed monotonic by
design
12
±0.5
±1
±0.25
10
±10
±1
±1.5
Bits
LSB
LSB
mV
mV
% of FSR
% of FSR
μV/°C
ppm
dB
μV
2
±1
−0.1
±2
±2.5
−100
10
Guaranteed monotonic by
design
All zeroes loaded to DAC
register
All ones loaded to DAC register
of FSR/°C
DAC code = midscale ; V
DD
±
10%
Due to full-scale output
change
R
L
= 2 kΩ to GND or V
DD
Due to load current change
Due to powering down (per
channel)
10
5
OUTPUT CHARACTERISTICS
3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
LOGIC INPUTS
3
Input Current
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
Pin Capacitance
10
5
μV/mA
μV
0
2
10
0.5
30
4
V
DD
0
2
10
0.5
30
4
V
DD
V
nF
nF
Ω
mA
μs
R
L
= ∞
R
L
= 2 kΩ
V
DD
= 5 V
Coming out of power-down
mode; V
DD
= 5 V
V
REF
= V
DD
= 5.5 V
170
0.75
26
200
V
DD
170
0.75
26
200
V
DD
μA
V
kΩ
μA
V
V
pF
±2
0.8
2
3
2
3
±2
0.8
All digital inputs
V
DD
= 5 V, 3 V
V
DD
= 5 V, 3 V
Rev. 0 | Page 3 of 24
AD5624/AD5664
Parameter
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
4
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
I
DD
(All Power-Down
Modes)
5
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
1
2
Min
2.7
A Grade
1
Typ
Max
5.5
0.45
0.44
0.9
0.85
Min
2.7
B Grade
1
Typ
Max
5.5
0.45
0.44
0.9
0.85
Unit
V
Conditions/Comments
V
IH
= V
DD
, V
IL
= GND
mA
mA
V
IH
= V
DD
, V
IL
= GND
0.48
0.2
1
1
0.48
0.2
1
1
μA
μA
Temperature range: A grade and B grade: −40°C to +105°C.
Linearity calculated using a reduced code range: AD5664 (Code 512 to Code 65,024); AD5624 (Code 32 to Code 4064); output unloaded.
3
Guaranteed by design and characterization, not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All DACs powered down.
AC CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; V
REF
= V
DD
; all specifications T
MIN
to T
MAX
, unless otherwise noted.
1
Table 3.
Parameter
2, 3
Output Voltage Settling Time
AD5664
AD5624
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
Output Noise
1
2
Min
Typ
4
3
1.8
10
0.1
−90
0.1
1
1
340
−80
120
100
15
Max
7
4.5
Unit
μs
μs
V/μs
nV-s
nV-s
dBs
nV-s
nV-s
nV-s
kHz
dB
nV/√Hz
nV/√Hz
μV
p-p
Conditions/Comments
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±0.5 LSB
1 LSB change around major carry
V
REF
= 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
V
REF
= 2 V ± 0.1 V p-p
V
REF
= 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = midscale, 1 kHz
DAC code = midscale, 10 kHz
0.1 Hz to 10 Hz
Guaranteed by design and characterization, not production tested.
Temperature range: −40°C to +105°C; typical at 25°C.
3
See the Terminology section.
Rev. 0 | Page 4 of 24
AD5624/AD5664
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2 (see Figure 2).
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter
t
1 2
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1
2
1
Limit at T
MIN
, T
MAX
V
DD
= 2.7 V to 5.5 V
20
9
9
13
5
5
0
15
13
0
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
Guaranteed by design and characterization, not production tested.
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V.
TIMING DIAGRAM
t
10
SCLK
t
1
t
9
t
2
t
8
SYNC
t
4
t
6
t
3
t
7
t
5
DIN
DB23
DB0
Figure 2. Serial Write Operation
Rev. 0 | Page 5 of 24
05943-002
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