ASM3P1819N
Product Preview
Low Power Mobile VGA EMI
Reduction IC
Description
The ASM3P1819N is a versatile spread spectrum frequency
modulator designed specifically for a wide range of input clock
frequencies from 20 to 40 MHz. The ASM3P1819N can generate an
EMI reduced clock from crystal, ceramic resonator, or system clock.
The ASM3P1819N reduces electromagnetic interference (EMI) at
the clock source, allowing a system wide EMI reduction for all the
down stream clocks and data dependent signals. The ASM3P1819N
allows significant system cost savings by reducing the number of
circuit board layers, ferrite beads, shielding, and other passive
components that are traditionally required to pass EMI regulations.
The ASM3P1819N modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, thereby decreasing the
peak amplitude of its harmonics. This results in a significantly lower
system EMI compared to the typical narrow band signal produced by
oscillators and most clock generators.
Lowering EMI by increasing a signal’s bandwidth is called “spread
spectrum clock generation”. The ASM3P1819N uses the most
efficient and optimized modulation profile approved by the FCC and
is implemented by using a proprietary all digital method.
Applications
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SOIC−8
S SUFFIX
CASE 751BD
TSSOP−8
T SUFFIX
CASE 948AL
PIN CONFIGURATION
XIN
VSS
NC
ModOUT
(Top View)
1
XOUT
VDD
PD#
REF
The ASM3P1819N is targeted towards EMI management for
memory and LVDS interfaces in mobile graphic chipsets and
high−speed digital applications such as PC peripheral devices,
consumer electronics and embedded controller system.
Features
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
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FCC Approved Method of EMI Attenuation
•
Provides up to 15 dB EMI Reduction
•
Generates a Low EMI Spread Spectrum Clock and a Non−spread
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Reference Clock of the Input Frequency
Optimized for Frequency Range from 20 MHz to 40 MHz
Internal Loop Filter Minimizes External Components and Board Space
Down Spread Deviation:
−1.25%
Low Inherent Cycle−to−Cycle Jitter
3.3 V Operating Voltage
CMOS/TTL Compatible Inputs and Outputs
Low Power CMOS Design
Supports Notebook VGA and Other LCD Timing Controller
Applications
Power Down Function for Mobile Application
Products are Available for Industrial Temperature Range
Available in 8 pin SOIC and TSSOP Packages
These are Pb−Free Devices
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. P2
1
Publication Order Number:
ASM3P1819N/D
ASM3P1819N
PD#
VDD
XIN
XOUT
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
REF
Modulation
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN
VSS
NC
ModOUT
REF
PD#
VDD
XOUT
Type
I
P
−
O
O
I
P
I
Description
Connect to externally generated Clock signal or Crystal.
Ground Connection. Connect to system ground.
No Connect.
Spread spectrum clock output.
Non−modulated Reference clock output of the input frequency.
Power down control pin. Pull LOW to enable Power−Down mode. This pin has an intern-
al pull−up resistor.
Connect to +3.3 V.
Connect to crystal. No connect if externally generated clock signal is used.
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD, V
IN
T
STG
T
A
T
s
T
J
T
DV
Parameter
Voltage on any pin with respect to Ground
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Rating
−0.5
to +4.6
−65
to +125
−40
to +85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. OUTPUT FREQUENCY AND MODULATION RATE
Input Frequency Range (MHz)
20 to 40
Output Frequency Range (MHz)
20 to 40
Modulation Rate
Input Frequency / 512
Spread Deviation (%)
−1.25
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2
ASM3P1819N
Table 4. DC ELECTRICAL CHARACTERISTICS
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
CC
I
DD
VDD
t
ON
Z
OUT
Input Low voltage
Input High voltage
Input Low current
Input High current
X
OUT
Output low current @ 0.4 V, VDD = 3.3 V
X
OUT
Output high current @ 2.5 V, VDD = 3.3 V
Output Low voltage VDD = 3.3 V, I
OL
= 20 mA
Output High voltage VDD = 3.3 V, I
OH
= 20 mA
Dynamic Supply current
3.3 V and 10 pF probe loading
Static Supply current
Operating Voltage
Power up time (First locked clock cycle after power up)
Clock Output impedance
2.5
7.1
f
IN
−
min
4.5
3.3
0.18
50
26.9
f
IN
−
max
mA
V
mS
W
3
3
0.4
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated.)
Parameter
Min
VSS
−
0.3
2.0
Typ
Max
0.8
VDD + 0.3
−20.0
1.0
Unit
V
V
mA
mA
mA
mA
V
V
mA
Table 5. AC ELECTRICAL CHARACTERISTICS
Symbol
f
IN
f
OUT
t
LH
(Note 1)
t
HL
(Note 1)
t
JC
t
D
Input Frequency
Output Frequency
Output Rise time (Measured from 0.8 V to 2.0 V)
Output Fall time (Measured from 2.0 V to 0.8 V)
Jitter (Cycle to Cycle)
Output Duty cycle
−200
45
50
Parameter
Min
20
20
0.69
0.66
200
55
Typ
Max
40
40
Unit
MHz
MHz
nS
nS
pS
%
1. t
LH
and t
HL
are measured into a capacitive load of 15 pF.
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3
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