Quad Channel, 128-/256-Position, I
2
C/SPI,
Nonvolatile Digital Potentiometer
Data Sheet
FEATURES
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: ±6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
Fast start-up time < 75 µs
Linear gain setting mode
Single- and dual-supply operation
Independent logic supply: 1.8 V to 5.5 V
Wide operating temperature: −40°C to +125°C
4 mm × 4 mm package option
AD5124/AD5144/AD5144A
FUNCTIONAL BLOCK DIAGRAM
V
LOGIC
V
DD
LRDAC
AD5124/AD5144
POWER-ON
RESET
RDAC1
INPUT
REGISTER 1
RESET
DIS
SCLK/SCL
SDI/SDA
SYNC/ADDR0
SDO/ADDR1
RDAC4
A4
A1
W1
B1
RDAC2
INPUT
REGISTER 2
SERIAL
INTERFACE
RDAC3
7/8
INPUT
REGISTER 3
A2
W2
B2
A3
W3
B3
APPLICATIONS
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
INPUT
REGISTER 4
EEPROM
MEMORY
W4
B4
GND
V
SS
WP
Figure 1.
AD5124/AD5144
24-Lead LFCSP
GENERAL DESCRIPTION
The
AD5124/AD5144/AD5144A
potentiometers provide a
nonvolatile solution for 128-/256-position adjustment applications,
offering guaranteed low resistor tolerance errors of ±8% and up to
±6 mA current density in the Ax, Bx, and Wx pins.
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals,
through the R
AW
and R
WB
string resistors, allowing very accurate
resistor matching.
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making these devices
suitable for filter design.
The low wiper resistance of only 40 Ω at the ends of the resistor
array allow for pin-to-pin connection.
The wiper values can be set through an SPI-/I
2
C-compatible digital
interface that is also used to read back the wiper register and
EEPROM contents.
The
AD5124/AD5144/AD5144A
are available in a compact,
24-lead, 4 mm × 4 mm LFCSP and a 20-lead TSSOP. The parts
are guaranteed to operate over the extended industrial temperature
range of −40°C to +125°C.
Table 1. Family Models
Model
AD5123
1
AD5124
AD5124
AD5143
1
AD5144
AD5144
AD5144A
AD5122
AD5122A
AD5142
AD5142A
AD5121
AD5141
1
Channel
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Dual
Dual
Dual
Dual
Single
Single
Position
128
128
128
256
256
256
256
128
128
256
256
128
256
Interface
I
2
C
SPI/I
2
C
SPI
I
2
C
SPI/I
2
C
SPI
I
2
C
SPI
I
2
C
SPI
I
2
C
SPI/I
2
C
SPI/I
2
C
Package
LFCSP
LFCSP
TSSOP
LFCSP
LFCSP
TSSOP
TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP
LFCSP
Two potentiometers and two rheostats.
Rev. C
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Trademarks and registered trademarks are the property of their respective owners.
10877-001
AD5124/AD5144/AD5144A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagrams—TSSOP ............................................ 3
Specifications..................................................................................... 4
Electrical Characteristics—AD5124 .......................................... 4
Electrical Characteristics—AD5144 and AD5144A ................ 7
Interface Timing Specifications ................................................ 10
Shift Register and Timing Diagrams ....................................... 11
Absolute Maximum Ratings .......................................................... 13
Thermal Resistance .................................................................... 13
ESD Caution ................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 17
Test Circuits ..................................................................................... 22
Theory of Operation ...................................................................... 23
Data Sheet
RDAC Register and EEPROM .................................................. 23
Input Shift Register .................................................................... 23
Serial Data Digital Interface Selection, DIS ............................ 23
SPI Serial Data Interface ............................................................ 23
I
2
C Serial Data Interface ............................................................ 25
I
2
C Address.................................................................................. 25
Advanced Control Modes ......................................................... 27
EEPROM or RDAC Register Protection ................................. 28
Load RDAC Input Register (LRDAC) ..................................... 28
RDAC Architecture .................................................................... 31
Programming the Variable Resistor ......................................... 31
Programming the Potentiometer Divider ............................... 32
Terminal Voltage Operating Range ......................................... 32
Power-Up Sequence ................................................................... 32
Layout and Power Supply Biasing ............................................ 32
Outline Dimensions ....................................................................... 33
Ordering Guide .......................................................................... 34
REVISION HISTORY
7/2019—Rev. B to Rev. C
Added Endnote 2, Table 14 ........................................................... 26
Added Endnote 2, Table 20 ........................................................... 29
Updated Outline Dimensions ....................................................... 33
7/2017—Rev. A to Rev. B
Changed LFCSP_WQ to LFCSP .................................. Throughout
Changes to Features Section............................................................ 1
Changes to Logic Supply Current Parameter, Table 2 ................. 5
Added Note 12 to Data Retention Parameter, Table 2;
Renumbered Sequentially................................................................ 6
Changes to Logic Supply Current Parameter, Table 3 ................. 8
Added Note 12 to Data Retention Parameter, Table 3;
Renumbered Sequentially................................................................ 9
Changes to Table 7.......................................................................... 13
Changes to Figure 11 and Table 11 .............................................. 16
Changes to Figure 20...................................................................... 18
Added Figure 21; Renumbered Sequentially .............................. 18
Changes to Figure 24...................................................................... 19
Change to Linear Gain Setting Mode Section ............................ 27
Change to RDAC Architecture Section ....................................... 31
Updated Outline Dimensions ....................................................... 33
12/2012—Rev. 0 to Rev. A
Changes to Table 12 and Table 13 ................................................ 25
10/2012—Revision 0: Initial Version
Rev. C | Page 2 of 36
Data Sheet
FUNCTIONAL BLOCK DIAGRAMS—TSSOP
V
LOGIC
V
DD
V
LOGIC
AD5124/AD5144/AD5144A
V
DD
AD5124/AD5144
POWER-ON
RESET
RDAC 1
INPUT
REGISTER 1
SYNC
SCLK
SDI
SDO
SPI
SERIAL
INTERFACE
RDAC 2
INPUT
REGISTER 2
RDAC 3
7/8
INPUT
REGISTER 3
RDAC 4
AD5144A
A1
W1
B1
A2
W2
B2
A3
W3
ADDR
SDA
RESET
SCL
I
2
C
SERIAL
INTERFACE
RDAC 2
INPUT
REGISTER 2
RDAC 3
8
INPUT
REGISTER 3
RDAC 4
POWER-ON
RESET
RDAC 1
INPUT
REGISTER 1
A1
W1
B1
A2
W2
B2
A3
W3
B3
A4
B3
A4
INPUT
REGISTER 4
EEPROM
MEMORY
10877-002
W4
B4
INPUT
REGISTER 4
EEPROM
MEMORY
W4
B4
GND
V
SS
GND
V
SS
Figure 2.
AD5124/AD5144
20-Lead TSSOP
Figure 3.
AD5144A
20-Lead TSSOP
Rev. C | Page 3 of 36
10877-003
AD5124/AD5144/AD5144A
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5124
Data Sheet
V
DD
= 2.3 V to 5.5 V, V
SS
= 0 V; V
DD
= 2.25 V to 2.75 V, V
SS
= −2.25 V to −2.75 V; V
LOGIC
= 1.8 V to 5.5 V, −40°C < T
A
< +125°C, unless
otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
Resistor Integral Nonlinearity
2
Symbol
Test Conditions/Comments
Min
Typ
1
Max
Unit
N
R-INL
7
R
AB
= 10 kΩ
V
DD
≥ 2.7 V
V
DD
< 2.7 V
R
AB
= 100 kΩ
V
DD
≥ 2.7 V
V
DD
< 2.7 V
−1
−2.5
−0.5
−1
−0.5
−8
±0.1
±1
±0.1
±0.25
±0.1
±1
35
55
130
40
60
±0.2
+1
+2.5
+0.5
+1
+0.5
+8
Bits
LSB
LSB
LSB
LSB
LSB
%
ppm/°C
Ω
Ω
Ω
Ω
%
Resistor Differential Nonlinearity
2
Nominal Resistor Tolerance
Resistance Temperature Coefficient
3
Wiper Resistance
3
R-DNL
ΔR
AB
/R
AB
(ΔR
AB
/R
AB
)/ΔT × 10
6
R
W
Code = full scale
Code = zero scale
R
AB
= 10 kΩ
R
AB
= 100 kΩ
R
AB
= 10 kΩ
R
AB
= 100 kΩ
Code = 0xFF
125
400
80
230
+1
Bottom Scale or Top Scale
R
BS
or R
TS
Nominal Resistance Match
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity
4
R
AB1
/R
AB2
−1
INL
R
AB
= 10 kΩ
R
AB
= 100 kΩ
−0.5
−0.25
−0.25
−1.5
−0.5
±0.1
±0.1
±0.1
−0.1
±0.1
1
0.25
±5
+0.5
+0.25
+0.25
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
Differential Nonlinearity
4
Full-Scale Error
DNL
V
WFSE
R
AB
= 10 kΩ
R
AB
= 100 kΩ
+0.5
1.5
0.5
Zero-Scale Error
V
WZSE
R
AB
= 10 kΩ
R
AB
= 100 kΩ
Code = half scale
Voltage Divider Temperature
Coefficient
3
(ΔV
W
/V
W
)/ΔT × 10
6
Rev. C | Page 4 of 36
Data Sheet
Parameter
RESISTOR TERMINALS
Maximum Continuous Current
Symbol
I
A
, I
B
, and I
W
R
AB
= 10 kΩ
R
AB
= 100 kΩ
Terminal Voltage Range
5
Capacitance A, Capacitance B
3
C
A
, C
B
f = 1 MHz, measured to GND,
code = half scale
R
AB
= 10 kΩ
R
AB
= 100 kΩ
f = 1 MHz, measured to GND,
code = half scale
R
AB
= 10 kΩ
R
AB
= 100 kΩ
V
A
= V
W
= V
B
Test Conditions/Comments
AD5124/AD5144/AD5144A
Min
Typ
1
Max
Unit
−6
−1.5
V
SS
+6
+1.5
V
DD
mA
mA
V
25
12
pF
pF
Capacitance W
3
C
W
Common-Mode Leakage Current
3
DIGITAL INPUTS
Input Logic
3
High
Low
Input Hysteresis
3
Input Current
3
Input Capacitance
3
DIGITAL OUTPUTS
Output High Voltage
3
Output Low Voltage
3
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
Positive Supply Current
−500
12
5
±15
+500
pF
pF
nA
V
INH
V
INL
V
HYST
I
IN
C
IN
V
OH
V
OL
V
LOGIC
= 1.8 V to 2.3 V
V
LOGIC
= 2.3 V to 5.5 V
0.8 × V
LOGIC
0.7 × V
LOGIC
0.2 × V
LOGIC
0.1 × V
LOGIC
±1
5
V
V
V
V
µA
pF
V
V
V
µA
pF
V
V
V
V
µA
nA
µA
mA
µA
µA
µW
dB
R
PULL-UP
= 2.2 kΩ to V
LOGIC
I
SINK
= 3 mA
I
SINK
= 6 mA, V
LOGIC
> 2.3 V
−1
V
LOGIC
0.4
0.6
+1
2
V
SS
= GND
Single supply, V
SS
= GND
Dual supply, V
SS
< GND
V
IH
= V
LOGIC
or V
IL
= GND
V
DD
= 5.5 V
V
DD
= 2.3 V
V
IH
= V
LOGIC
or V
IL
= GND
V
IH
= V
LOGIC
or V
IL
= GND
V
IH
= V
LOGIC
or V
IL
= GND
V
IH
= V
LOGIC
or V
IL
= GND
V
IH
= V
LOGIC
or V
IL
= GND
∆V
DD
/∆V
SS
= V
DD
± 10%,
code = full scale
2.3
±2.25
1.8
2.25
0.7
400
−0.7
2
320
0.05
3.5
−66
5.5
±2.75
V
DD
V
DD
5.5
I
DD
Negative Supply Current
EEPROM Store Current
3, 6
EEPROM Read Current
3, 7
Logic Supply Current
Power Dissipation
8
Power Supply Rejection Ratio
I
SS
I
DD_EEPROM_STORE
I
DD_EEPROM_READ
I
LOGIC
P
DISS
PSRR
−5.5
1.4
−60
Rev. C | Page 5 of 36
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