http://www.elm-tech.com
GD25Q128C
DATASHEET
GD25Q128CxIGx
3.3V Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
- Content -
1. FEATURES
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2. GENERAL DESCRIPTION
3. MEMORY ORGANIZATION
4. DEVICE OPERATION
5. DATA PROTECTION
6. STATUS REGISTER
Page
4
5
6
7
9
11
13
18
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19
20
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34
35
36
37
38
40
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42
43
44
7. COMMANDS DESCRIPTION
7.1. Write Enable (WREN) (06H)
7.2. Write Disable (WRDI) (04H)
7.3. Write Enable for Volatile Status Register (50H)
7.4. Read Status Register (RDSR) (05H or 35H or 15H)
7.5. Write Status Register (WRSR) (01H or 31H or 11H)
7.6. Read Data Bytes (READ) (03H)
7.8. Dual Output Fast Read (3BH)
7.9. Quad Output Fast Read (6BH)
7.10. Dual I/O Fast Read (BBH)
7.11. Quad I/O Fast Read (EBH)
7.13. Set Burst with Wrap (77H)
7.14. Page Program (PP) (02H)
7.15. Quad Page Program (32H)
7.16. Sector Erase (SE) (20H)
7.17. 32KB Block Erase (BE) (52H)
7.18. 64KB Block Erase (BE) (D8H)
7.19. Chip Erase (CE) (60/C7H)
7.20. Deep Power-Down (DP) (B9H)
7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)
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7.12. Quad I/O Word Fast Read (E7H)
7.21. Release from Deep Power-Down and Read Device ID (RDI) (ABH)
7.22. Read Manufacture ID/Device ID (REMS) (90H)
7.23. Read Manufacture ID/Device ID Dual I/O (92H)
7.24. Read Manufacture ID/Device ID Quad I/O (94H)
7.25. Read Identification (RDID) (9FH)
7.26. Program/Erase Suspend (PES) (75H)
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69 - 2
Rev.1.1
GD25Q128CxIGx
3.3V Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.27. Program/Erase Resume (PER) (7AH)
7.28. Erase Security Registers (44H)
7.29. Program Security Registers (42H)
7.30. Read Security Registers (48H)
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45
46
47
48
49
51
53
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55
56
57
62
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69
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7.31. Individual Block/Sector Lock (36H)/Unlock (39H)/Read (3DH)
7.32. Global Block/Sector Lock (7EH) or Unlock (98H)
7.33. Set Read Parameters (C0H)
7.34. Burst Read With Wrap (0CH)
7.35. Enable QPI (38H)
7.36. Disable QPI (FFH)
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7.37. Enable Reset (66H) and Reset (99H)
8. ELECTRICAL CHARACTERISTICS
8.1. Power-ON timing
8.2. Initial Delivery State
7.38. Read Serial Flash Discoverable Parameter (5AH)
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8.3. Data Retention and Endurance
8.4. Absolute Maximum Ratings
8.6. DC Characteristics
8.7. AC Characteristics
8.5. Capacitance Measurement Conditions
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9. ORDERING INFORMATION
10. PACKAGE INFORMATION
10.1. Package SOP8 208MIL
10.2. Package WSON8 (6×5MM)
69 - 3
Rev.1.1
GD25Q128CxIGx
3.3V Uniform Sector Dual and Quad Serial Flash
1. FEATURES
♦
128M-bit Serial Flash
- 16384K-byte
- 256 bytes per programmable page
http://www.elm-tech.com
♦
Program/Erase Speed
- Page Program time: 0.6ms typical
- Sector Erase time: 50ms typical
- Block Erase time: 0.2/0.3s typical
- Chip Erase time: 60s typical
♦
Standard, Dual, Quad SPI
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#/RESET#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/RESET#
♦
Flexible Architecture
- Sector of 4K-byte
- Block of 32/64K-byte
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
- QPI: SCLK, CS#, IO0, IO1, IO2, IO3
♦
High Speed Clock Frequency
- 104MHz for Standard and Dual SPI fast read with 30PF load
♦
Low Power Consumption
- 20mA maximum active current
- 5μA maximum power down current
- 80MHz for Quad SPI and QPI fast read with 30PF load
- Dual I/O Data transfer up to 208Mbits/s
♦
Advanced Security Features
(1)
- Quad I/O Data transfer up to 320Mbits/s
- 3×512-Byte Security Registers With OTP Locks
- QPI Mode Data transfer up to 320Mbits/s
- Discoverable parameters(SFDP) register
- Continuous Read With 8/16/32/64-byte Wrap
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Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Enable/Disable protection with WP# pin
- Top or Bottom, Sector or Block selection
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Single Power Supply Voltage
- Full voltage range: 2.7~3.6V
♦ Package
Information
- SOP8 (208mil)
- WSON8 (6×5mm)
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Cycling endurance
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Minimum 100,000 Program/Erase Cycles
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Data retention
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20-year data retention typical.
Note: (1) Please contact ELM for details.
69 - 4
Rev.1.1
GD25Q128CxIGx
3.3V Uniform Sector Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
http://www.elm-tech.com
The GD25Q128C(128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports
the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#) and I/O3 (HOLD#/
RESET#). The Dual I/O data is transferred with speed of 208Mbits/s and the Quad I/O & Quad Output data is
transferred with speed of 320Mbits/s.
Connection Diagram
CS#
SO
WP#
VSS
1
2
3
4
8–LEAD
8-LEAD
SOP
SOP
8
7
6
5
VCC
HOLD#/
RESET#
SCLK
SI
CS#
SO
1
2
8
VCC
Top View
Top View
7
HOLD#/
RESET#
6 SCLK
5
SI
WP# 3
VSS 4
8–LEAD WSON
8-LEAD WSON
Pin Description
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD#/RESET (IO3)
VCC
Block Diagram
WP#(IO2)
Write Control
Logic
I/O
I
I/O
I/O
I/O
I
I/O
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold or Reset Input (Data Input Output 3)
Power Supply
Write Protect Logic
and Row Decode
Status
Register
HOLD#
RESET#(IO3)
SCLK
CS#
SI(IO0)
SO(IO1)
SPI
Command &
Control Logic
High Voltage
Generators
Flash
Memory
Page Address
Latch/Counter
Column Decode And
256-Byte Page Buffer
Byte Address
Latch/Counter
69 - 5
Rev.1.1
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