http://www.elm-tech.com
GD25Q41B
DATASHEET
GD25Q41BxIGx
Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
- Content -
1. FEATURES
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2. GENERAL DESCRIPTION
3. MEMORY ORGANIZATION
4. DEVICE OPERATION
5. DATA PROTECTION
6. STATUS REGISTER
Table of ID Definition
Page
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Rev.1.1
7. COMMANDS DESCRIPTION
7.1. Write Enable (WREN) (06H)
7.2. Write Disable (WRDI) (04H)
7.3. Write Enable for Volatile Status Register (50H)
7.4. Read Status Register (RDSR) (05H or 35H)
7.5. Write Status Register (WRSR) (01H)
7.6. Write Status Register (WRSR) (31H)
7.7. Read Data Bytes (READ) (03H)
7.9. Dual Output Fast Read (3BH)
7.10. Quad Output Fast Read (6BH)
7.11. Dual I/O Fast Read (BBH)
7.12. Quad I/O Fast Read (EBH)
7.14. Set Burst with Wrap (77H)
7.15. Page Program (PP) (02H)
7.16. Sector Erase (SE) (20H)
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7.8. Read Data Bytes at Higher Speed (Fast Read) (0BH)
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7.13. Quad I/O Word Fast Read (E7H)
7.17. 32KB Block Erase (BE) (52H)
7.18. 64KB Block Erase (BE) (D8H)
7.19. Chip Erase (CE) (60/C7H)
7.20. Deep Power-Down (DP) (B9H)
7.21. Release from Deep Power-Down or High Performance Mode and Read Device ID (RDI) (ABH) 29
7.22. Read Manufacture ID/Device ID (REMS) (90H)
7.23. Read Manufacture ID/Device ID Dual I/O (92H)
7.24. Read Manufacture ID/Device ID Quad I/O (94H)
7.25. Read Identification (RDID) (9FH)
7.26. High Performance Mode (HPM) (A3H)
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46 - 2
GD25Q41BxIGx
Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.27. Erase Security Registers (44H)
7.28. Program Security Registers (42H)
7.29. Read Security Registers (48H)
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7.30. Continuous Read Mode Reset (CRMR) (FFH)
7.31. Program/Erase Suspend (PES) (75H)
7.32. Program/Erase Resume (PER) (7AH)
8. ELECTRICAL CHARACTERISTICS
8.1. Power-ON timing
8.2. Initial delivery state
8.4. Latch up characteristics
8.5. Absolute maximum ratings
8.7. DC characteristics
8.8. AC characteristics
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8.3. Data retention and endurance
8.6. Capacitance measurement conditions
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9. ORDERING INFORMATION
10. PACKAGE INFORMATION
10.1. Package SOP8 150MIL
10.2. Package SOP8 208MIL
10.3. Package USON8 (3x2MM)
46 - 3
Rev.1.1
GD25Q41BxIGx
Uniform Sector Dual and Quad Serial Flash
1. FEATURES
♦
4M-bit Serial Flash
- 512K-byte
- 256 bytes per programmable page
http://www.elm-tech.com
♦
Program/Erase Speed
- Page Program time: 0.35ms typical
- Sector Erase time: 50ms typical
- Block Erase time: 0.18/0.25s typical
- Chip Erase time: 1.5s typical
♦
Standard, Dual, Quad SPI
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
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Flexible Architecture
- Sector of 4K-byte
- Block of 32/64K-byte
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High Speed Clock Frequency
- 104MHz for fast read with 30PF load
- Dual I/O Data transfer up to 208Mbits/s
- Quad I/O Data transfer up to 416Mbits/s
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Low Power Consumption
- 20mA maximum active current
- 5μA maximum power down current
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Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Enable/Disable protection with WP# pin
- Top or Bottom, Sector or Block selection
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Single Power Supply Voltage
- Full voltage range: 2.7~3.6V
♦ Minimum 100,000 Program/Erase Cycles
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Advanced security Features
- Power Supply Lock-Down
- 3×512-Byte Security Registers With OTP Locks
- Volatile and Non-volatile Status Register Bits
46 - 4
Rev.1.1
GD25Q41BxIGx
Uniform Sector Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
http://www.elm-tech.com
The GD25Q41B Serial flash supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2
(WP#), and I/O3 (HOLD#). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock
rates of 208MHz for Dual Output & Dual I/O read command, and 416MHz for Quad output & Quad I/O read
command.
Connection Diagram
8-LEAD SOP
Pin Description
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD# (IO3)
VCC
Block Diagram
WP#(IO2)
Write Control
Logic
8-LEAD USON
I/O
I
I/O
I/O
I/O
I
I/O
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
Write Protect Logic
and Row Decode
Status
Register
HOLD#(IO3)
SCLK
CS#
SI(IO0)
SO(IO1)
High Voltage
Generators
Page Address
Latch/Counter
SPI
Command &
Control Logic
Flash
Memory
Column Decode And
256-Byte Page Buffer
Byte Address
Latch/Counter
46 - 5
Rev.1.1
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