Data Sheet No.PD60217 revB
IR2011(
S) & (PbF
)
HIGH AND LOW SIDE DRIVER
Features
·
·
·
·
·
·
·
·
·
Floating channel designed for bootstrap operation
Fully operational up to +200V
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10V to 20V
Independent low and high side channels
Input logicHIN/LIN active high
Undervoltage lockout for both channels
3.3V and 5V input logic compatible
CMOS Schmitt-triggered inputs with pull-down
Matched propagation delay for both channels
Also available LEAD-FREE (PbF)
Product Summary
V
OFFSET
I
O
+/-
V
OUT
t
on/off
Delay Matching
200V max.
1.0A /1.0A typ.
10 - 20V
80 & 60 ns typ.
20 ns max.
Applications
·
Audio Class D amplifiers
·
High power DC-DC SMPS converters
·
Other high frequency applications
Packages
Description
The IR2011 is a high power, high speed power MOSFET driver with independent high
and low side referenced output channels, ideal for Audio Class D and DC-DC converter
applications. Logic inputs are compatible with standard CMOS or LSTTL output, down
to 3.0V logic. The output drivers feature a high pulse current buffer stage designed for
minimum driver cross-conduction. Propagation delays are matched to simplify use in
high frequency applications. The floating channel can be used to drive an N-channel
power MOSFET in the high side configuration which operates up to 200 volts. Propri-
etary HVIC and latch immune CMOS technologies enable ruggedized monolithic con-
struction.
8-Lead SOIC
IR2011S
Typical Connection
8-Lead PDIP
IR2011
200V
HIN
LIN
COM
5
HIN
LIN
COM
V
S
4
HO
V
B
V
CC
1
TO
LOAD
8
LO
V
CC
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please
refer to our Application Notes and DesignTips for proper circuit board layout.
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1
IR2011(S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
dV
s
/dt
P
D
R
THJA
T
J
T
S
T
L
Definition
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side fixed supply voltage
Low side output voltage
Logic input voltage (HIN & LIN)
Allowable offset supply voltage transient (figure 2)
Package power dissipation @ T
A
£
+25°C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
(8-lead DIP)
(8-lead SOIC)
(8-lead DIP)
(8-lead SOIC)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
-0.3
—
—
—
—
—
—
-55
—
Max.
225
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+0.3
V
CC
+0.3
50
1.0
0.625
125
200
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. The VS and COM offset ratings
are tested with all supplies biased at 15V differential.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
T
A
Definition
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side fixed supply voltage
Low side output voltage
Logic input voltage (HIN & LIN)
Ambient temperature
Min.
V
S
+ 10
Note 1
V
S
10
0
COM
-40
Max.
V
S
+ 20
200
V
B
20
V
CC
5.5
125
Units
V
°C
Note 1: Logic operational for V
S
of -4 to +200V. Logic state held for V
S
of -4V to -V
BS
.
2
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IR2011(S) & (PbF)
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, C
L
= 1000 pF, T
A
= 25°C unless otherwise specified. Figure 1 shows the timing definitions.
Symbol
t
on
t
off
t
r
t
f
DM1
DM2
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
Turn-on delay matching | t
on
(H) - t
on
(L) |
Turn-off delay matching | t
off
(H) - t
off
(L) |
Min. Typ. Max. Units Test Conditions
—
—
—
—
—
—
80
75
35
20
—
—
—
—
50
35
20
20
V
S
= 0V
V
S
= 200V
ns
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, and T
A
= 25°C unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to
COM and are applicable to all logic input leads: HIN and LIN. The V
O
and I
O
parameters are referenced to COM and are
applicable to the respective output leads: HO or LO.
Symbol
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
BSUV+
V
BSUV-
V
CCUV+
V
CCUV-
I
O+
I
O-
Definition
Logic “1” input voltage
Logic “0” input voltage
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Logic “1” input bias current
Logic “0” input bias current
V
BS
supply undervoltage positive going
threshold
V
BS
supply undervoltage negative going
threshold
V
CC
supply undervoltage positive going
threshold
V
CC
supply undervoltage negative going
threshold
Output high short circuit pulsed current
Output low short circuit pulsed current
Min. Typ. Max. Units Test Conditions
2.2
—
—
—
—
—
—
—
—
8.2
7.4
8.2
7.4
—
—
—
—
—
—
—
90
140
7.0
—
9.0
8.2
9.0
8.2
1.0
1.0
—
0.7
2.0
0.2
50
210
230
20
1.0
9.8
9.0
V
9.8
9.0
—
—
A
V
O
= 0V,
PW
£
10
µs
V
O
= 15V,
PW
£
10
µs
µA
V
I
O
= 0A
20mA
V
B
=V
S
= 200V
V
IN
= 0V or 3.3V
V
IN
= 0V or 3.3V
V
IN
= 3.3V
V
IN
= 0V
V
CC
= 10V - 20V
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3
IR2011(S) & (PbF)
Functional Block Diagram
V
B
HIGH
VOLTAGE
LEVEL
SHIFT
CIRCUIT
UV
DETECT
UV Q
S
R
V
S
3V S-TRIGGER
HIN
LOW
VOLTAGE
LEVEL
SHIFT
BUFFER
HO
V
CC
3V S-TRIGGER
LIN
LOW
VOLTAGE
LEVEL
SHIFT
UV
DETECT
LO
DELAY
COM
Lead Definitions
Symbol Description
HIN
LIN
V
B
HO
V
S
V
CC
LO
COM
Logic input for high side gate driver output (HO), in phase
Logic input for low side gate driver output (LO), in phase
High side floating supply
High side gate drive output
High side floating supply return
Low side supply
Low side gate drive output
Low side return
Lead Assignments
5
HIN
6
LIN
7
COM
8
LO
V
S
4
HO
3
V
B
2
V
CC
1
5
HIN
6
LIN
7
COM
8
LO
V
S
4
HO
3
V
B
2
V
CC
1
8-Lead PDIP
8-Lead SOIC
IR2011
Part Number
4
IR2011S
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IR2011(S) & (PbF)
50%
50%
HIN / LIN
t
rise
90%
t
on
(H)
10%
90%
t
fall
t
off
(H)
10%
HO
DM1
90%
t
on
(L)
10%
t
off
(L)
DM2
LO
Figure 1. Timing Diagram
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