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LUPXA255A0E400

Description
32-BIT, 400 MHz, MICROPROCESSOR, PBGA256
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size885KB,41 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Environmental Compliance
Download Datasheet Parametric View All

LUPXA255A0E400 Overview

32-BIT, 400 MHz, MICROPROCESSOR, PBGA256

LUPXA255A0E400 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerIntel
Parts packaging codeBGA
package instructionBGA, BGA256,16X16,40
Contacts256
Reach Compliance Codeunknow
Address bus width26
bit size32
boundary scanYES
maximum clock frequency3.6864 MHz
External data bus width32
FormatFIXED POINT
Integrated cacheYES
JESD-30 codeS-PBGA-B256
JESD-609 codee1
length17 mm
low power modeYES
Number of terminals256
Maximum operating temperature100 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA256,16X16,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)250
power supply1.3,2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height2 mm
speed400 MHz
Maximum supply voltage1.64 V
Minimum supply voltage1.235 V
Nominal supply voltage1.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature40
width17 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR
Intel® PXA255 Processor
Electrical, Mechanical, and Thermal Specification
Data Sheet
Product Features
High Performance Processor
— Intel® XScale™ Microarchitecture
— 32 KB Instruction Cache
— 32 KB Data Cache
— 2 KB “mini” Data Cache
— Extensive Data Buffering
Intel® Media Processing Technology
— Enhanced 16-bit Multiply
— 40-bit Accumulator
Flexible Clocking
— CPU clock from 100 to 400 MHz
— Flexible memory clock ratios
— Frequency change modes
Rich Serial Peripheral Set
— AC97 Audio Port
— I
2
S Audio Port
— USB Client Controller
— High Speed UART
— Second UART with flow control
— UART with hardware flow control
— FIR and SIR infrared comm ports
Low Power
— Less than 500 mW Typical Internal
Dissipation
— Supply Voltage may be Reduced to
1.00 V
— Low Power/Sleep Modes
High Performance Memory Controller
— Four Banks of SDRAM - up to 100 MHz
— Five Static Chip Selects
— Support for PCMCIA or Compact Flash
— Companion Chip interface
Additional Peripherals for system
connectivity
— Multimedia Card Controller (MMC)
— SSP Controller
— Network SSP controller for baseband
— I2C Controller
— Two Pulse Width Modulators (PWMs)
— All peripheral pins double as GPIOs
Hardware debug features
Hardware Performance Monitoring features
Order Number: 278805-002
February, 2004

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