MMFT3055V
Power MOSFET
1 Amp, 60 Volts
N−Channel SOT−223
These Power MOSFETs are designed for low voltage, high speed
switching applications in power supplies, converters and power motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
Features
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1 AMPERE, 60 VOLTS
R
DS(on)
= 130 mW
N−Channel
D
•
Avalanche Energy Specified
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
•
Pb−Free Package is Available
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MW)
Gate−to−Source Voltage
−
Continuous
−
Non−repetitive (t
p
≤
10 ms)
Drain Current
−
Continuous
Drain Current
−
Continuous @ 100°C
Drain Current
−
Single Pulse (t
p
≤
10
ms)
Total PD @ T
A
= 25°C mounted on 1″ sq.
Drain pad on FR−4 bd material
Total PD @ T
A
= 25°C mounted on
0.70″ sq. Drain pad on FR−4 bd material
Total PD @ T
A
= 25°C mounted on min.
Drain pad on FR−4 bd material
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy
−
Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 10 Vdc, Peak
I
L
= 3.4 Apk, L = 10 mH, R
G
= 25
W
)
Thermal Resistance
−
Junction to Ambient on 1″ sq.
Drain padon FR−4 bd material
−
Junction to Ambient on 0.70″ sq.
Drain pad on FR−4 bd material
−
Junction to Ambient on min.
Drain pad on FR−4 bd material
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 s
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
Value
60
60
±
20
±
25
1.7
1.4
6.0
2.1
1.7
0.94
6.3
T
J
, T
stg
E
AS
58
°C/W
−55
to
175
mW/°C
°C
mJ
Unit
Vdc
Vdc
1
G
S
4
Vdc
Vpk
Adc
Apk
W
2
TO−261AA
CASE 318E
STYLE 3
3
I
DM
P
D
MARKING DIAGRAM AND
PIN ASSIGNMENT
4 Drain
AYW
V3055
G
G
1
Gate
2
Drain
3
Source
R
qJA
R
qJA
R
qJA
T
L
70
88
159
260
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
V3055 = Device Code
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
°C
MMFT3055VT1
MMFT3055VT1G
Package
SOT−223
SOT−223
(Pb−Free)
Shipping
†
1000 Tape & Reel
1000 Tape & Reel
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
MMFT3055V/D
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 4
1
MMFT3055V
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 60 Vdc, V
GS
= 0 Vdc)
(V
DS
= 60 Vdc, V
GS
= 0 Vdc, T
J
= 150°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 1)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 0.85 Adc)
Drain−to−Source On−Voltage
(V
GS
= 10 Vdc, I
D
= 1.7 Adc)
(V
GS
= 10 Vdc, I
D
= 0.85 Adc, T
J
= 150°C)
Forward Transconductance (V
DS
= 8.0 Vdc, I
D
= 1.7 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 48 Vdc, I
D
= 1.7 Adc,
V
GS
= 10 Vdc)
(V
DD
= 30 Vdc, I
D
= 1.7 Adc,
V
GS
= 10 Vdc, R
G
= 9.1
W)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 1)
(I
S
= 1.7 Adc, V
GS
= 0 Vdc)
(I
S
= 1.7 Adc, V
GS
= 0 Vdc, T
J
= 150°C)
V
SD
−
−
−
−
−
−
0.85
0.7
40
34
6.0
0.089
1.6
−
−
−
−
−
mC
nH
nH
Vdc
−
−
−
−
−
−
−
−
8.0
9.0
32
18
13
2.0
5.0
4.0
20
20
60
40
20
−
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
360
110
25
500
150
50
pF
(Cpk
≥
2.0) (Note 3)
V
GS(th)
2.0
−
−
−
−
1.0
2.8
5.6
0.115
−
−
2.7
4.0
−
0.13
0.27
0.25
−
Vdc
mV/°C
W
Vdc
(Cpk
≥
2.0) (Note 3)
V
(BR)DSS
60
−
−
−
−
−
63
−
−
−
−
−
10
100
100
Vdc
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
(Cpk
≥
2.0) (Note 3)
R
DS(on)
V
DS(on)
g
FS
mhos
Reverse Recovery Time
(I
S
= 1.7 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
1. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
2. Switching characteristics are independent of operating junction temperature.
Max limit
−
Typ
3. Reflects typical values.
C
pk
=
3 x SIGMA
t
rr
t
a
t
b
Q
RR
L
D
L
S
ns
−
−
4.5
7.5
−
−
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2
MMFT3055V
TYPICAL ELECTRICAL CHARACTERISTICS
4
I D , DRAIN CURRENT (AMPS)
3.5
3
2.5
2
1.5
1
0.5
0
0
1
6
7
8
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
2
4V
3.5 V
9
10
4.5 V
4
3.5
I D , DRAIN CURRENT (AMPS)
3
2.5
2
1.5
1
0.5
0
2
2.5
3
3.5
4
100°C
25°C
T
J
= − 55°C
4.5
5
5.5
6
6.5
7
7.5
V
GS
= 10 V
7V
6V
5.5 V
T
J
= 25°C
5V
V
DS
≥
10 V
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.25
0.225
0.2
T
J
= 100°C
25°C
− 55°C
V
GS
= 10 V
0.170
0.155
T
J
= 25°C
0.175
0.15
0.140
0.125
0.110
V
GS
= 10 V
15 V
0.125
0.1
0.095
0.080
0.075
0.05
0
0.025
0
0.5
1
1.5
3
2.5
2
I
D
, DRAIN CURRENT (AMPS)
3.5
4
0.065
0.050
0
0.5
1
1.5
3
2
2.5
I
D
, DRAIN CURRENT (AMPS)
3.5
4
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2.0
1.8
1.6
V
GS
= 10 V
I
D
= 0.85 A
I DSS , LEAKAGE (nA)
1000
V
GS
= 0 V
T
J
= 125°C
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
− 50
− 25
0
25
50
75
100 125
T
J
, JUNCTION TEMPERATURE (°C)
150
175
100
100°C
10
0
5
10 15 20 25 30 35 40 45 50
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
55
60
Figure 5. On−Resistance Variation with
Temperature
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3
Figure 6. Drain−To−Source Leakage
Current versus Voltage
MMFT3055V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
1100
1000
900
C, CAPACITANCE (pF)
800
700
600
500
400
300
200
100
0
10
5
V
GS
0
V
DS
5
C
rss
10
15
20
25
C
oss
C
iss
C
rss
C
iss
V
DS
= 0 V
V
GS
= 0 V
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
T
J
= 25°C
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
MMFT3055V
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
10
9
8
7
6
5
4
3
2
1
0
0
Q3
2
4
6
8
10
V
DS
12
Q
T
, TOTAL CHARGE (nC)
I
D
= 1.7 A
T
J
= 25°C
Q1
Q2
V
GS
QT
30
27
24
21
18
15
12
9
6
3
0
14
1000
V
DD
= 30 V
I
D
= 1.7 A
V
GS
= 10 V
T
J
= 25°C
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
100
t
d(off)
10
t
d(on)
t
f
t
r
1
1
10
R
G
, GATE RESISTANCE (OHMS)
100
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
2
1.8
I S , SOURCE CURRENT (AMPS)
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
V
GS
= 0 V
T
J
= 25°C
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (T
C
) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded and the
transition time (t
r
,t
f
) do not exceed 10
ms.
In addition the total
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
−
T
C
)/(R
qJC
).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous I
D
can safely be
assumed to equal the values indicated.
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