CCD Image Digitizers with
CDS, PGA and 12-Bit A/D
June 2003
XRD98L63
FEATURES
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12-bit Resolution ADC, 30MHz Sampling Rate
10-bit Programmable Gain: 6dB to 36dB PGA
Pixel-by-pixel gain switching
Digitally Controlled Black Level Calibration with
Pixel Averager and Hot Pixel Clipper
DNS Filter Removes Black Level Digital Noise
Programmable Black Level, up to code 255
Black Level Calibration Range: 300 mV
Programmable Aperture Delays
1.0 ns/step for SBLK & SPIX
0.5 ns/step for ADCLK
Manual Control of Offset DACs via Serial Port
for use with High-speed Scanners
Single 2.7V to 3.6V Power Supply
Optimize power with external resistor to 100mW
Low Power for Battery Operation
100µA Stand-by Mode Current
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Three-state Digital Outputs
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3,000V ESD Protection
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48-pin TQFP Package
APPLICATIONS
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Mega pixel Digital Still Cameras
Digital Camcorders
3 CCD Professional/Broadcast Camera
Line Scan Cameras
PC Video Cameras
CCTV/Security Cameras
Industrial/Medical Cameras
2D Bar Code Readers
High Speed Scanners
Digital Copiers
GENERAL DESCRIPTION
The XRD98L63 is a complete, low power CCD Image
Digitizer for digital motion and still cameras. The
product includes a high bandwidth differential Corre-
lated Double Sampler (CDS), 10-bit Programmable
Gain Amplifier (PGA) with pixel rate gain switching, 12-
bit Analog-to-Digital Converter (ADC) and improved
digitally controlled black level auto-calibration circuitry
with programmable pixel averaging, hot pixel clipping,
and a Digital Noise Suppression (DNS) filter.
The Correlated Double Sampler (CDS) subtracts the
CCD output signal black level from the video level.
Common mode and power supply noise are rejected by
the differential CDS input stage.
The PGA is digitally controlled with 10-bit resolution on
a dB scale, resulting in a gain range of 6dB to 36dB with
0.047dB per LSB of the gain code. The PGA can be
programmed to switch gain every pixel, in a user
defined pattern of up to 4 different gains. Our propri-
etary control logic allows a camera system to set the
desired gain ratios for color balance. The system gain
can then be changed by writing to a single register,
and the color balance will be maintained.
The black level auto-calibration circuit averages the
results of the Optical Black pixels to compensate for
any internal offset of the XRD98L63 as well as black
level offset from the CCD. The calibration logic uses
proprietary digital filters to eliminate line-to-line offset
noise and noise due to hot pixels in the Optical Black
areas.
The PGA and black level auto-calibration are con-
trolled through a simple 3-wire serial interface. The
timing circuitry is designed to enable users to select a
wide variety of available CCD and image sensors for
their applications. Readback of the serial data regis-
ters is available from the digital output bus.
The XRD98L63 is packaged in 48-lead TQFP to reduce
space and weight, and is suitable for hand-held and
portable applications.
ORDERING INFORMATION
Part No.
XRD98L63AIV
Package
48-Pin TQFP
Temperature Range
-40°C to 85°C
Operating
Power Supply
2.7V to 3.6V
Maximum
Sampling Rate
30 MSPS
Rev.1.01
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
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(510) 668-7000
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FAX (510) 668-7017
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www.exar.com
XRD98L63
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
OVDD
OGND
DGND
ADCLK
DVDD
EOS
PBLK
CAL
SBLK
SPIX
CLAMP
FSYNC
AGND
AGND
AVDD
N/C
REFIN
CCDIN
N/C
VCM
AVDD
N/C
AGND
N/C
BIASRES
CAPP
CAPN
AVDD
AGND
OE
RESET
PD
TESTOUT
LOAD
SDI
SCLK
Type
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Power
Ground
Ground
Digital in
Power
Digital in
Digital in
Digital in
Digital in
Digital in
Digital in
Digital in
Ground
Ground
Power
Analog
Analog
Analog
Power
Ground
Analog
Analog
Analog
Power
Ground
Digital in
Digital in
Digital in
Digital out
Digital in
Digital in
Digital in
Description
ADC Output (LSB)
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output (MSB)
Digital Output Power Supply (must be < AVDD )
Digital Output Ground
On chip Logic Ground
ADC Clock
On chip Logic Power Supply (must = AVDD)
Even/Odd Line select
Pre-Blanking clock
Calibration Control Clock (clamp OB)
CDS Sample Black Clock
CDS Sample Pixel Clock
DC-Restore Input Clamp Control Clock
Frame Sync Clock
Analog Ground
Analog Ground
Analog Power Supply
(Not used)
CCD Reference Signal
CCD Input Signal
(Not used)
Common mode bias by-pass
Analog Power Supply
(Not used)
Analog Ground
(not used)
External Reference Resistor (connect 18.2KΩ resistor to ground)
ADC Reference By-Pass
ADC Reference By-Pass
Analog Power Supply
Analog Ground
Output Enable Control, 1=high-Z, 0=enable, internal pull down
Reset Control, 1=convert, 0=reset, internal pull up
Power Down Control, 1=Power Down, 0=convert, internal pull down
Factory Test Output
Serial Interface Data Load
Serial Interface Data Input
Serial Interface Shift Clock
Rev.1.01
3
XRD98L63
DC ELECTRICAL CHARACTERISTICS – XRD98L63 (cont'd)
Unless otherwise specified: OV
DD
= DV
DD
=AV
DD
= 3.0V, Pixel Rate = 30MSPS, T
A
= 25°C
Rext = 18.2 KΩ
Symbol
Parameter
Min.
Typ. Max.
Unit
Conditions
System Specifications
DNL
S
f
smax
f
smin
e
n
e
n
MAXAV
MINAV
System DNL
Maximum Sample Rate
Minimum Sample Rate
Input ref. Noise, max.Gain
Input ref. Noise, min.Gain
Pipeline Delay
30
+0.6
+1.0
LSB
MSPS
No missing codes, monotonic
500
180
400
7.5
KSPS
µV
rms
µV
rms
cycles
Not tested
Gain Code = 640 (36db)
Gain Code = 0 (6dB)
Latency
Digital Inputs (Digital Input Thresholds are Set by DV
DD
)
V
IH
V
IL
I
L
I
L
I
L
I
L
C
IN
Digital Outputs
V
OH
V
OL
I
OZ
Digital Output High Voltage
Digital Output Low Voltage
High–Z Leakage
0.05
OV
DD
-0.5
Digital Input High Voltage
Digital Input Low Voltage
DC Leakage Current
Input Leakage, PD and OE
Input Leakage, RESET
Input Leakage, All Other
Digital Inputs
Input Capacitance
V
DD
-0.5
GND+0.5
V
V
µA
µA
µA
nA
pF
V
IN
between GND and V
DD.
PD and OE have internal pull-down
resisters
RESET has an internal pull-up
resister
Input = V
DD
or GND
0.05
-5
-100
-100
5
±1.0
100
5
100
V
0.5
±1.0
V
µA
While sourcing 2mA
While sinking 2mA
OE = 1 or PD = 1 or OE bit = 0
Rev.1.01
5
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