DDR2 SDRAM SO-DIMM
HYMP112S64(L)M8
DESCRIPTION
128Mx64 bits
Hynix HYMP112S64M8 series is unbuffered 200-pin double data rate 2 Synchronous DRAM Small Outline Dual In-
Line Memory Modules (DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMP112S64M8
series consists of eight 128Mx8 DDR2 SDRAMs in 63 ball FBGA Dual Die Pacakge(DDP)s. Hynix HYMP112S64M8
series provide a high performance 8-byte interface in 67.60mm X 30.00mm form factor of industry standard. It is suit-
able for easy interchange and addition.
Hynix HYMP512S64M8 series is designed for high speed and offers fully synchronous operations referenced to both
rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising
edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 4-bit prefetched to achieve very high bandwidth. All input and output volt-
age levels are compatible with SSTL_1.8. High speed frequencies, programmable latencies and burst lengths allow
variety of device operation in high performance memory system.
Hynix HYMP512S64M8 series incorporates SPD(serial presence detect). Serial presence detect function is imple-
mented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
•
1GB (128M x 64) Unbuffered DDR2 SO - DIMM
based on 128Mx8 DDR2 DDP SDRAMs
JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
All inputs and outputs are compatible with SSTL_1.8
interface
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
Fully differential clock operations (CK & /CK)
•
•
•
•
•
Programmable CAS Latency 3 / 4 /5 supported
Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
Auto refresh and self refresh supported
7.8us refresh period at Lower than T
CASE
85℃,
3.9us( 85
℃ ＜
T
CASE
≤ 95℃)
Serial Presence Detect(SPD) with EEPROM
•
•
•
ORDERING INFORMATION
Type
Part No.
HYMP112S64(L)M8-E4
PC2-3200 (DDR2-400)
HYMP112S64(L)M8-E3
HYMP112S64(L)M8-C5
PC2-4300 (DDR2-533)
HYMP112S64(L)M8-C4
4-4-4
2 rank 1GB
SO-DIMM
3-3-3
5-5-5
Description
CL-tRCD-tRP
4-4-4
Form Factor
200pin Unbuffered SO-
DIMM
67.60 mm x 30,00 mm
(MO-224)
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2/July 2004
2
HYMP112S64(L)M8
PIN Functional Description
Symbol
CK[1:0],
CK[1:0]
Type
Input
Polarity
Cross Point
Pin Description
The system clock inputs. All adress an commands lines are sampled on the cross point of
the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the com-
mand decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by
S1
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS
and WE define the operation to be excecuted by the SDRAM.
Selects which DDR2 SDRAM internal bank of four or eight is activated.
Active High
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
During a Bank Activate command cycle, difines the row address when sampled at the cross
point of the rising edge of CK and falling edge of CK. During a Read or Write command
cycle, defines the column address when sampled at the cross point of the rising edge of CK
and falling edge of CK. In addition to the column address, AP is used to invoke autopre-
charge operation at the end of the burst read or write cycle. If AP is high., autoprecharge
is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is
disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to
control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of
the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to
precharge.
Data Input/Output pins.
Active High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect.
The data strobe, associated with one data byte, sourced whit data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window. In
Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of
the data window. DQS signals are complements, and timing is relative to the crosspoint of
respective DQS and DQS. If the module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers
programmed approriately.
When hign, the PLL outputs are always driven when the PLL input clock is active. When
low, the PLL remains locked on the input clock, if active, but output clocks are stopped.
Pulled high via 10Kߟ resistor on the SO-DIMM . Only used on DDR2 SO-DIMMs with a
PLL.
Power supplies for core, I/O, Serial Presense Detect, and ground for the module.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister
must be connected to V
DD t
o act as a pull up.
This signals is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from SCL to VDD to act as a pull up.
Address pins used to select the Serial Presence Detect base address.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory
modules(SODIMMs).
CKE[1:0]
Input
Active High
/S[1:0]
/RAS, /CAS, /
WE
BA[1:0]
ODT[1:0]
Input
Active Low
Input
Input
Input
Active Low
A[9:0], A10/
AP, A[15:11]
Input
DQ[63:0]
DM[7:0]
In/Out
Input
DQS[7:0],
DQS[7:0]
In/Out
Cross point
RESET
V
DD
,
V
DD
SPD,V
SS
SDA
SCL
SA[1:0]
TEST
Input
Active Low
Supply
In/Out
Input
Input
In/Out
Rev. 0.2/ July 2004
3
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