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74LVC1G17GV

Description
8-Bit Addressable Latches 16-TSSOP -40 to 85
Categorylogic    logic   
File Size81KB,16 Pages
ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.)
Websitehttps://www.nxp.com/
Download Datasheet Parametric Compare View All

74LVC1G17GV Overview

8-Bit Addressable Latches 16-TSSOP -40 to 85

74LVC1G17GV Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerPhilips Semiconductors (NXP Semiconductors N.V.)
package instructionTSOP, TSOP5/6,.11,37
Reach Compliance Codeunknow
JESD-30 codeR-PDSO-G5
JESD-609 codee0
Load capacitance (CL)50 pF
Logic integrated circuit typeBUFFER
MaximumI(ol)0.024 A
Number of terminals5
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP
Encapsulate equivalent codeTSOP5/6,.11,37
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
method of packingTAPE AND REEL
power supply3.3 V
Prop。Delay @ Nom-Su7 ns
Certification statusNot Qualified
Schmitt triggerYES
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.95 mm
Terminal locationDUAL
Base Number Matches1
INTEGRATED CIRCUITS
DATA SHEET
74LVC1G17
Single Schmitt-trigger buffer
Product specification
Supersedes data of 2004 Oct 18
2004 Nov 30

74LVC1G17GV Related Products

74LVC1G17GV 74LVC1G17 74LVC1G17GM 74LVC1G17GW
Description 8-Bit Addressable Latches 16-TSSOP -40 to 85 8-Bit Addressable Latches 16-TSSOP -40 to 85 8-Bit Addressable Latches 16-TSSOP -40 to 85 LVC/LCX/Z SERIES, 1-INPUT NON-INVERT GATE, PDSO5
Is it Rohs certified? incompatible - incompatible incompatible
Maker Philips Semiconductors (NXP Semiconductors N.V.) - Philips Semiconductors (NXP Semiconductors N.V.) Philips Semiconductors (NXP Semiconductors N.V.)
package instruction TSOP, TSOP5/6,.11,37 - SON, SOLCC6,.04,20 TSSOP, TSSOP5/6,.08
Reach Compliance Code unknow - unknow unknow
JESD-30 code R-PDSO-G5 - R-PDSO-N6 R-PDSO-G5
JESD-609 code e0 - e0 e0
Load capacitance (CL) 50 pF - 50 pF 50 pF
Logic integrated circuit type BUFFER - BUFFER BUFFER
MaximumI(ol) 0.024 A - 0.024 A 0.024 A
Number of terminals 5 - 6 5
Maximum operating temperature 125 °C - 125 °C 125 °C
Minimum operating temperature -40 °C - -40 °C -40 °C
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSOP - SON TSSOP
Encapsulate equivalent code TSOP5/6,.11,37 - SOLCC6,.04,20 TSSOP5/6,.08
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE - SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing TAPE AND REEL - TAPE AND REEL TAPE AND REEL
power supply 3.3 V - 3.3 V 3.3 V
Prop。Delay @ Nom-Su 7 ns - 7 ns 7 ns
Certification status Not Qualified - Not Qualified Not Qualified
Schmitt trigger YES - YES YES
Nominal supply voltage (Vsup) 3.3 V - 3.3 V 3.3 V
surface mount YES - YES YES
technology CMOS - CMOS CMOS
Temperature level AUTOMOTIVE - AUTOMOTIVE AUTOMOTIVE
Terminal surface Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form GULL WING - NO LEAD GULL WING
Terminal pitch 0.95 mm - 0.5 mm 0.635 mm
Terminal location DUAL - DUAL DUAL
Base Number Matches 1 - 1 1
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