F1953
DATASHEET
6-bit Digital Step Attenuator
400 to 4000 MHz IDTF1953
G
ENERAL
D
ESCRIPTION
This document describes the specification for the
IDTF1953 Digital Step Attenuator. The F1953 is part of a
family of
Glitch-Free
TM
DSAs optimized for the demanding
requirements of communications Infrastructure. These
devices are offered in a compact 4x4 QFN package with
50
Ω
impedances for ease of integration.
F
EATURES
Glitch-Free
TM
, < 0.6 dB transient overshoot
C
OMPETITIVE
A
DVANTAGE
Digital step attenuators are used in Receivers and
Transmitters to provide gain control. The IDTF1953 is a
6-bit step attenuator optimized for these demanding
applications. The silicon design has very low insertion
loss and low distortion (> +60 dBm IP3
I
.) The device
has pinpoint accuracy and settles to final attenuation
value within 400 nsec. Most importantly, the F1953
includes IDT’s
Glitch-Free
TM
technology which results in
less than 0.5 dB of overshoot ringing during MSB
transitions. This is in stark contrast to competing DSAs
that
glitch as much as 10 dB
(see p. 10.)
Lowest insertion loss for best SNR
Glitch-Free
TM
when transitioning – won’t
damage PA or ADC
Extremely accurate with low distortion
TM
Glitch-Free
TM
Spurious Free Design
2.7 to 3.3 V supply
Attenuation Error < 0.5 dB @ 2 GHz
Low Insertion Loss < 1.4 dB @ 2 GHz
Excellent Linearity >+60 dBm IP3
I
Fast settling time, < 400 nsec
Serial or Parallel Interface 31.5 dB Range
Stable Integral Non-Linearity over temperature
Low Power Consumption < 200 uA
Integrated DC blocking capacitors
Drop-In replacement
4x4 mm Thin QFN 20 pin package
D
EVICE
B
LOCK
D
IAGRAM
RF
1
RF
2
A
PPLICATIONS
Base Station 2G, 3G, 4G, TDD radiocards
Repeaters and E911 systems
Digital Pre-Distortion
Point to Point Infrastructure
Public Safety Infrastructure
WIMAX Receivers and Transmitters
Military Systems, JTRS radios
RFID handheld and portable readers
Cable Infrastructure
V
MODE
V
DD
D[5:0]
CLK DATA LE
6
Bias
DEC
SPI
O
RDERING
I
NFORMATION
Omit IDT
prefix
0.8 mm height
package
Tape &
Reel
P
ART
# M
ATRIX
Part#
Freq range
Resolution
/ Range
0.25 / 31.75
0.50 / 31.5
0.50 / 15.5
0.50 / 31.5
Control
Parallel &
Serial
Serial Only
Serial Only
Parallel &
Serial
IL
Pinout
PE43702
PE43701
HMC305
HMC305
PE4302
DAT-31R5
IDTF1953NCGI8
RF product Line
Green
Industrial
Temp range
F1950
F1951
F1952
F1953
150 - 4000
100 - 4000
100 – 4000
400 - 4000
-1.3
-1.2
-0.9
-1.3
Glitch-Free
TM
Digital Step Attenuator
1
Rev2 April2014
F1953
DATASHEET
6-bit Digital Step Attenuator
400 to 4000 MHz IDTF1953
A
BSOLUTE
M
AXIMUM
R
ATINGS
V
DD
to GND
D[5:0], DATA, CLK,LE,V
MODE
RF Input Power (RF1, RF2) calibration and testing
RF Input Power (RF1, RF2) continuous RF operation
θ
JA
(Junction – Ambient)
θ
JC
(Junction – Case)
The Case is defined as the exposed paddle
Operating Temperature Range (Case Temperature)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (soldering, 10s) .
-0.3V to +3.3V
-0.3V to 3.6V
+29 dBm
+23 dBm
+50°C/W
+3°C/W
T
C
= -40°C to +100°C
140°C
-65°C to +150°C
+260°C
Stresses above those listed above may cause permanent damage to the device. Functional operation of the device at
these or any other conditions above those indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD Caution
This product features proprietary protection circuitry. However, it may be damaged if
subjected to high energy ESD. Please use proper ESD precautions when handling to
avoid damage or loss of performance.
Glitch-Free
TM
Digital Step Attenuator
2
Rev2 April2014
F1953
DATASHEET
6-bit Digital Step Attenuator
400 to 4000 MHz IDTF1953
IDTF1953 S
PECIFICATION
(31.5 dB Range)
Specifications apply at
V
DD
= +3.0V, f
RF
= 2000MHz,
T
C
= +25°C, V
MODE
> V
IH
(Serial Mode) EVkit losses are de-embedded (see p. 17)
Parameter
Logic Input High
Logic Input Low
Logic Current
Logic Current
Supply Voltage(s)
Supply Current
Temperature Range
Frequency Range
RF1,RF2 Return Loss
Minimum Attenuation
Maximum Attenuation
Minimum Gain Step
Phase Delta
Differential ATTN Error
Integral ATTN Error
Integral ATTN Error
Comment
CLK, CSb, SDI, SDO, RSTb
CLK, CSb, SDI, SDO, RSTb
Sym.
V
IH
V
IL
I
IH,
I
IL
I
IH,
I
IL
V
DD
I
DD
T
C
f
RF
S
11,
S
22
A
MIN
A
MAX
LSB
Φ
Δ
DNL
INL
1
INL
2
IP3I
1
IP3I
2
IP3I
3
min
0.7xV
DD
typ
max
V
DD
0.3xV
DD
units
V
V
μA
μA
V
mA
degC
MHz
dB
V
MODE
, D[5:0]
LE
Main Supply
-5
-35
2.7 to 3.3
+5
+35
0.16
-40 to +100
400 to 4000
Total V
DD
= 3V
Operating Range
(Case)
Operating Range
20*log(S
11
),
20*log(S
22
)
D[5:0] = [000000]
D[5:0] = [111111]
Least Significant Bit
Phase change A
MIN
vs. A
MAX
0.25
1
-23
1.35
32.0
32.4
0.50
39
0.09
0.20
0.47
+57
2
1.90
dB
dB
dB
deg
dB
Between adjacent steps
Error vs. line (A
MIN
ref) to
13.5dB ATTN
Error vs. line (A
MIN
ref) to
31.5dB ATTN
0.60
0.75
dB
dB
D[5:0] = [000000] = A
MIN
D[5:0] = [011111] = A
15.5
+66
+60
+60
+53
+53
Input IP3
D[5:0] = [111111] = A
MAX
P
IN
= +10 dBm per tone
50 MHz Tone Separation
dBm
0.1 dB Compression
Please note ABS MAX P
IN
on Page 2
Settling Time
(parallel mode)
Serial Clock Speed
Serial Setup Time
Clock width
LE setup time
LE pulse
D[5:0] = [000101] = A
2.5
Baseline P
IN
= 20 dBm
Start LE rising edge > V
IH
End +/-0.10 dB Pout settling
15.5 – 16.0 transition
P
0.1
T
LSB
F
CLK
A
B
C
D
20
10
10
30
28.5
400
10
50
dBm
nsec
MHz
ns
ns
ns
ns
SPI 3 wire bus
From rising edge of Vmode to
rising edge of CLK for D5
Clock high pulse width
From rising edge of CLK pulse
for D0 to LE rising edge
LE minimum pulse width
S
PECIFICATION
N
OTES
:
1 – Items in min/max columns in
bold italics
are Guaranteed by Test
2 – All other Items in min/max columns are Guaranteed by Design Characterization
Glitch-Free
TM
Digital Step Attenuator
3
Rev2 April2014
F1953
DATASHEET
6-bit Digital Step Attenuator
400 to 4000 MHz IDTF1953
S
ERIAL
C
ONTROL
Serial mode is selected when V
MODE
is pulled high (> V
IH
), In serial mode the F1953 attenuation setting is programmed
via the 3 wire bus (LE, CLK, DATA). In serial mode data is clocked in MSB first. Note the timing diagram below.
Note
–
The IDTF1953 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device
is not being programmed. When Latch enable is high (> V
IH
), the CLK input is disabled and DATA will not be clocked
into the shift register. It is recommended that LE be pulled high (> V
IH
) when the device is not being programmed.
S
ERIAL
R
EGISTER
D
EFAULT
C
ONDITION
If the device is powered up in Serial Mode, the device will default to whatever attenuation state is defined by the six
parallel data input pins D5,D4,D3,D2,D1,D0 thus allowing
any attenuation setting
to be specified as the power up state.
S
ERIAL
R
EGISTER
T
IMING
D
IAGRAM
:
(Note the Timing Spec Intervals in
Blue)
V
MODE
1
2
3
4
5
6
7
8
9
CLK
Spec
Interval
A
B
C
D
Data Word
Latched into
Active Register
LE
Data Word 6 bits
DATA
16 dB
8 dB
4 dB
2 dB
1 dB
0.5 dB
Time
D5
MSB
D4
D3
D2
D1
D0
LSB
Polarity:
1 = Attenuation switched IN
0 = Attenuation switched OU
T
S
ERIAL
R
EGISTER
T
IMING
T
ABLE
Interval
Symbol
A
B
C
D
Description
From rising edge of Vmode to rising edge of CLK for D5
Clock high pulse width
From rising edge of CLK pulse for D0 to LE rising edge
LE minimum pulse width
Min
Spec
20
10
10
30
Max
Spec
Units
nsec
nsec
nsec
nsec
Glitch-Free
TM
Digital Step Attenuator
4
Rev2 April2014
F1953
DATASHEET
6-bit Digital Step Attenuator
400 to 4000 MHz IDTF1953
P
ARALLEL
C
ONTROL
M
ODE
The user has the option of running in one of two parallel modes:
Direct Parallel Mode
or
Latched Parallel
Mode.
D
IRECT
-P
ARALLEL
M
ODE
:
Direct-parallel mode is selected when V
MODE
(pin 13) is < V
IL
and LE (pin 5) is > V
IH
. In this mode the
device will immediately react to any voltage changes to the parallel control pins [pins 1, 15, 16, 17, 19, 20].
Use direct-parallel mode for the fastest settling time.
L
ATCHED
-P
ARALLEL
M
ODE
:
Latched-parallel mode is selected when V
MODE
(pin 13) is < V
IL
and LE (pin 5) is toggled from < V
IL
to > V
IH
To utilize latched-parallel mode:
Set LE < V
IL
Adjust pins [1, 15, 16, 17, 19, 20] to the desired attenuation setting. (Note the device will not react
to these pins while LE < V
IL
.)
Pull LE > V
IH
. The device will then transition to the attenuation settings reflected by these pins.
When the device is powered up In Latched Parallel Mode [V
MODE
< V
IL
and LE < V
IL
], the attenuation setting
defaults to the state defined by the six parallel data pins [pins 1, 15, 16, 17, 19, 20]
L
ATCHED
P
ARALLEL
M
ODE
T
IMING
D
IAGRAM
:
(Note the Timing Spec Intervals in
Blue)
V
MODE
Spec
Interval
s
A
D
C
B
Data Word
Latched into
Active Register
LE
D[5: 0]
L
ATCHED
P
ARALLEL
M
ODE
T
IMING
T
ABLE
:
Interval
Symbol
A
B
C
D
Description
Serial to Parallel Mode Setup Time
Parallel Data Hold Time
LE minimum pulse width
Parallel Data Setup Time
Min
Spec
100
10
10
10
Max
Spec
Units
nsec
nsec
nsec
nsec
Glitch-Free
TM
Digital Step Attenuator
5
Rev2 April2014
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