P2041A
Versatile EMI Reduction IC
Description
The P2041A is a selectable spread spectrum frequency modulator
designed specifically for PC peripheral and embedded controller
markets. The P2041A reduces electromagnetic interference (EMI) at
the clock source which provides system wide reduction of EMI of all
clock dependent signals. The P2041A allows significant system cost
savings by reducing the number of circuit board layers and shielding
that are traditionally required to pass EMI regulations.
The P2041A uses the most efficient and optimized modulation
profile approved by the FCC and is implemented in a proprietary
all−digital method.
The P2041A modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock and, more importantly,
decreases the peak amplitudes of its harmonics. This results in
significantly lower system EMI compared to the typical narrow band
signal produced by oscillators and most frequency generators.
Lowering EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation.’
Applications
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SOIC−8
S SUFFIX
CASE 751BD
TSSOP−8
T SUFFIX
CASE 948AL
PIN CONFIGURATION
XIN / CLK
XOUT
SR1
VSS
(Top View)
1
VDD
P2041A
SR0
ModOUT
SSON
The P2041A is targeted towards the embedded controller market
and PC peripheral markets including scanners, MFP’s, printers, PDA,
IA, and GPS devices.
Features
•
FCC Approved Method of EMI Attenuation
•
Provides up to 20 dB of EMI Suppression
•
Generates a Low EMI Spread Spectrum Clock of the Input
•
•
•
•
•
•
•
•
•
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Frequency
Optimized for 25 MHz to 60 MHz Input Frequency Range
Internal Loop Filter Minimizes External Components and Board
Space
4 Selectable Spread Ranges
SSON Control Pin for Spread Spectrum Enable and Disable Options
Low Cycle−to−Cycle Jitter
3.3 V or 5.0 V Operating Voltage
Low Power CMOS Design
Available in 8−pin SOIC and TSSOP Packages
These are Pb−Free Devices
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. 2
1
Publication Order Number:
P2041A/D
P2041A
SR0
SR1 SSON
VDD
XIN
XOUT
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Modulation
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Figure 1. Block Diagram
Table 1. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD, V
IN
T
STG
T
A
T
s
T
J
T
DV
Parameter
Voltage on any pin with respect to Ground
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Rating
−0.5
to +7.0
−65
to +125
−40
to +85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 2. PIN DESCRIPTION
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN / CLK
XOUT
SR1
VSS
SSON
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
Connect to crystal or externally generated clock signal.
Connect to crystal. No connect if externally generated clock signal is used.
Digital logic input used to select Spreading Range (see Table 3).
This pin has an internal pull−up resistor.
Ground Connection. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active Low).
Spread Spectrum function enable when low. This pin has an internal pull−low resistor.
Spread Spectrum Clock Output.
Digital logic input used to select Spreading Range (see Table 3).
This pin has an internal pull−up resistor.
Connect to +3.3 V or +5.0 V.
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2
P2041A
Table 3. SPREAD RANGE SELECTION
SR1
0
0
1
1
SR0
0
1
0
1
Spreading Range
±1.50%
±2.50%
±0.50%
±1.00%
Modulation rate
(Fin/40)*34.72 KHz
(Fin/40)*34.72 KHz
(Fin/40)*34.72 KHz
(Fin/40)*34.72 KHz
Spread Spectrum Selection
Table 3 illustrates the possible spread spectrum options.
The optimal setting should minimize system EMI to the
fullest without affecting system performance. The spreading
is described as a percentage deviation of the center
frequency (Note: The center frequency is the frequency of
the external reference input on XIN / CLK, Pin 1).
Example of a typical printer or scanner application
that operates on a clock frequency of 40 MHz:
A spreading selection of SR1=1 and SR0=1 provides a
percentage deviation of
±1.00%*
(see Table 3) of Center
Frequency. This results in the frequency on ModOUT being
swept from 40.40 MHz to 39.60 MHz at a modulation rate
of (40/40)*34.72 = 34.72 KHz (see Table 3). This particular
example (see Figure below) given here is a common EMI
reduction method for scanners and has already been
implemented by most of the leading manufacturers.
NOTE:
Spreading range selection varies from different system
manufacturers and their designs. The spreading range of
P2041A can be set to
±2.5%
when working with certain
scanner model.
VDD
40 MHz
1 XIN / CLK VDD 8
2 XOUT
3 SR1
SR0 7
ModOUT 6
0.1
mF
SSON 5
4 VSS
P2041A
Modulated 40 MHz signal with
±1.00%
Deviation and modulation rate of
34.72 KHz. This signal is connected back
to the clock crystal Input pin of the system
ASIC.
Note: The above schematic indicates The
exact setting of this example: Default set-
ting (no connection on pin 3, 7 and 5).
Figure 2. P2041A Application Schematic for Flat−Bed Scanner
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P2041A
Table 4. DC ELECTRICAL CHARACTERISTICS
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
VDD
Input low Voltage
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated.)
Parameter
(For 3.3 V Supply Voltage)
(For 5 V Supply Voltage)
Input low Voltage
(For 3.3 V Supply Voltage)
(For 5 V Supply Voltage)
Input Low Current
(pull−up resistor on inputs SR0, SR1)
Input High Current
(pull−down resistor on input SSON)
(For 3.3 V Supply Voltage)
(For 5 V Supply Voltage)
(For 3.3 V Supply Voltage)
(For 5 V Supply Voltage)
Min
VSS−0.3
−
2.0
3.5
−
−
−
−
−
−
−
−
2.5
4.5
−
3.3 V and 15 pF loading
5 V and 15 pF loading
Operating Voltage
−
−
2.7
Typ
−
−
−
−
−
−
−
−
3
3
−
−
−
−
1.0
−
−
3.3
Max
0.8
1.5
VDD+0.3
−
−35
−100
35
100
−
−
0.4
0.5
−
−
−
22
35
5.5
V
mA
mA
V
mA
mA
V
mA
mA
V
Unit
V
XOUT Output Low Current (V
XOL
@ 0.4 V, VDD = 3.3 V)
XOUT Output High Current (V
XOH
@ 2.5 V, VDD = 3.3 V)
Output Low Voltage
(VDD = 3.3 V, I
OL
= 20 mA)
(VDD = 5 V, I
OL
= 20 mA)
Output High Voltage
(VDD = 3.3 V, I
OH
= 20 mA)
(VDD = 5 V, I
OH
= 20 mA)
Static Supply Current
Dynamic Supply Current
Table 5. AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Input Frequency
Output rise time (Measured at 0.8 V to 2.0 V)
Output fall time (Measured at 2.0 V to 0.8 V)
Jitter (Cycle−to−cycle)
Output duty cycle
Min
25
0.7
0.6
−
45
Typ
40
1.0
0.8
360
50
Max
60
1.3
1.0
−
55
Unit
MHz
nS
nS
pS
%
f
IN
t
LH
(Note 1)
t
HL
(Note 1)
t
JC
t
D
1. t
LH
and t
HL
are measured into a capacitive load of 15 pF.
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P2041A
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
A
A1
A2
b
E1
E
c
D
E
E1
e
L
L1
MIN
0.05
0.80
0.19
0.09
2.90
6.30
4.30
NOM
MAX
1.20
0.15
0.90
1.05
0.30
0.20
3.00
6.40
4.40
0.65 BSC
1.00 REF
3.10
6.50
4.50
0.50
0.60
0.75
θ
e
0º
8º
TOP VIEW
D
A2
A
q1
c
A1
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
L1
END VIEW
L
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