IDTF1950
DATASHEET
7-bit 0.25 dB Digital Step Attenuator
150 MHz to 4000 MHz
G
ENERAL
D
ESCRIPTION
This document describes the specification for the
IDTF1950 Digital Step Attenuator. The F1950 is part of a
family of
Glitch-Free
TM
DSAs optimized for the demanding
requirements of communications Infrastructure. These
devices are offered in a compact 4x4 QFN package with
50 impedances for ease of integration into the radio
system.
F
EATURES
•
•
•
•
•
•
•
•
•
•
Glitch-Free
TM
, < 0.6 dB transient overshoot
Spurious Free Design
3V to 5V supply
Attenuation Error < 0.3 dB @ 2 GHz
Low Insertion Loss < 1.3 dB @ 2 GHz
Excellent Linearity +65 dBm IP3
I
Fast settling time, < 400 nsec
Class 2 JEDEC ESD (> 2kV HBM)
Serial & Parallel Interface 31.75 dB Range
4x4 mm Thin QFN 24 pin package
C
OMPETITIVE
A
DVANTAGE
Digital step attenuators are used in Receivers and
Transmitters to provide gain control. The IDTF1950 is a
7-bit step attenuator optimized for these demanding
applications. The silicon design has very low insertion
loss and low distortion (+65 dBm IP3
I
.) The device has
pinpoint accuracy and settles to final attenuation value
within 400 nsec. Most importantly, the F1950 includes
IDT’s
Glitch-Free
TM
technology which results in less
than 0.6 dB of overshoot ringing during MSB transitions.
This is in stark contrast to competing DSAs that
glitch as
much as 10 dB
during MSB transitions (see p.10)
D
EVICE
B
LOCK
D
IAGRAM
Lowest insertion loss for best SNR
Glitch-Free
TM
when transitioning –
won’t damage PA or ADC
Extremely accurate with low distortion
TM
Glitch-Free
TM
RF
1
RF
2
A
PPLICATIONS
•
•
•
•
•
•
•
•
•
Base Station 2G, 3G, 4G, TDD radiocards
Repeaters and E911 systems
Digital Pre-Distortion
Point to Point Infrastructure
Public Safety Infrastructure
WIMAX Receivers and Transmitters
Military Systems, JTRS radios
RFID handheld and portable readers
Cable Infrastructure
Bias
DEC
SPI
7
V
MODE
V
DD
D[6:0]
CLK DATA LE
O
RDERING
I
NFORMATION
Omit IDT
prefix
0.8 mm height
package
Tape &
Reel
P
ART
# M
ATRIX
Part#
Freq range
Resolution
/ Range
0.25 / 31.75
0.50 / 31.5
0.50 / 15.5
Control
Parallel &
Serial
Serial Only
Serial Only
IL
Pinout
F 1950
F1951
F1952
150 - 4000
100 - 4000
100 – 4000
- 1 .3
-1.2
-0.9
PE
HITT
HITT
IDTF1950NBGI8
RF product Line
Green
Industrial
Temp range
Glitch-Free
TM
Digital Step Attenuator
1
Rev1 March 2012
IDTF1950
DATASHEET
7-bit 0.25 dB Digital Step Attenuator
150 MHz to 4000 MHz
A
BSOLUTE
M
AXIMUM
R
ATINGS
V
DD
to GND
D[6:0], DATA, CLK,LE, V
MODE
RF Input Power (RF1, RF2) calibration and testing
RF Input Power (RF1, RF2) continuous RF operation
θ
JA
(Junction – Ambient)
θ
JC
(Junction – Case)
The Case is defined as the exposed paddle
Operating Temperature Range (Case Temperature)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (soldering, 10s) .
-0.3V to +5.25V
-0.3V to 3.6V
+29 dBm
+23 dBm
+50°C/W
+3°C/W
T
C
= -40°C to +100°C
140°C
-65°C to +150°C
+260°C
Glitch-Free
TM
Digital Step Attenuator
2
Rev1 March 2012
IDTF1950
DATASHEET
7-bit 0.25 dB Digital Step Attenuator
150 MHz to 4000 MHz
IDTF1950 S
PECIFICATION
(31.75 dB Range)
Specifications apply at
V
DD
= +3.3V, f
RF
= 2000MHz,
and T
C
= +25°C, EVkit losses are de-embedded (see p. 17) for spec purposes
Parameter
Logic Input High
Logic Input Low
Logic Current
Supply Voltage(s)
Supply Current
Temperature Range
Frequency Range
RF1, RF2 Return Loss
Minimum Attenuation
Maximum Attenuation
Minimum Gain Step
Phase Delta
Differential Non-Linearity
Integral Non-Linearity
Integral Non-Linearity
Comment
CLK, LE, DATA, D[6:0], V
MODE
CLK, LE, DATA, D[6:0], V
MODE
Sym.
V
IH
V
IL
I
IH,
I
IL
V
DD
I
DD
T
C
f
RF
S
11
, S
22
A
MIN
or
IL
A
MAX
LSB
Φ
∆
DNL
INL
1
INL
2
IP3I
1
IP3I
2
IP3I
3
min
2.3
-5
typical
max
3.6
0.7
+5
units
V
V
µA
V
mA
degC
MHz
dB
V
MODE
Main Supply
3.0 to 5.25
0.25
-40 to +100
150 to 4000
-22
1.3
32.6
33.0
0.25
34
0.10
0.02
0.27
+60
2
Total
Operating Range
(Case)
Operating Range
dB(s11), dB(s22)
D[6:0] = [0000000]
D[6:0] = [1111111]
Least Significant Bit
Phase change A
MIN
vs. A
MAX
0.5
1
1.9
dB
dB
dB
deg
dB
Max error between
adjacent steps
Max Error vs. line (A
MIN
ref) to
13.75 dB ATTN
Max Error vs. line (A
MIN
ref) to
31.75 dB ATTN
0.30
0.45
dB
dB
D[6:0] = [0000000] = A
MIN
D[6:0] = [0111111] = A
15.75
+63
+61
+61
+59
+57
Input IP3
D[6:0] = [1111111] = A
MAX
P
IN
= +10 dBm per tone
50 MHz Tone Separation
dBm
0.1 dB Compression
Please note ABS MAX
Input power on Page 2
D[6:0] = [0001010] = A
2.5
Baseline P
IN
= 20 dBm
Start LE rising edge > V
IH
End +/-0.10 dB Pout settling
15.75 – 16.00 transition
P
0.1
T
LSB
F
CLK
A
B
C
100
10
10
27.5
400
20
50
dBm
nsec
MHz
ns
ns
ns
Settling Time
Serial Clock Speed
Parallel to Serial Setup
Serial Data Hold Time
LE delay from final
serial clock rising edge
SPI 3 wire bus
SPI 3 wire bus
SPI 3 wire bus
SPI 3 wire bus
S
PECIFICATION
N
OTES
:
1 – Items in min/max columns in
bold italics
are Guaranteed by Test
2 – All other Items in min/max columns are Guaranteed by Design Characterization
Glitch-Free
TM
Digital Step Attenuator
3
Rev1 March 2012
IDTF1950
DATASHEET
7-bit 0.25 dB Digital Step Attenuator
150 MHz to 4000 MHz
S
ERIAL
C
ONTROL
M
ODE
Serial mode is selected by floating V
MODE
(pin3) or pulling it to a voltage > V
IH
. In serial mode data is clocked in LSB
first. Note the timing diagram below.
Note
–
The IDTF1950 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device
is not being programmed. When Latch enable is high (> V
IH
), the CLK input is disabled and DATA will not be clocked
into the shift register. It is recommended that LE be pulled high (> V
IH
) when the device is not being programmed.
S
ERIAL
R
EGISTER
T
IMING
D
IAGRAM
:
(Note the Timing Spec Intervals in
Blue)
V
MODE
1
2
3
4
5
6
7
8
9
CLK
Spec
Interval
A
B
C
Data Word
Latched into
Active Register
LE
Data Word 8 bits
DATA
0.25 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
16 dB
X
D0
LSB
D1
D2
D3
D4
D5
D6
MSB
D7
RSV
Time
S
ERIAL
M
ODE
D
EFAULT
C
ONDITION
:
When the device is powered up it will default to the
Maximum Attenuation
setting as described below:
Note that for the F1950 in all cases (High or 1) = Attenuation Stepped IN. (0 or Low) = Attenuation Stepped OUT.
Default Register Settings
0
D7
RSV
1
D6
MSB
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
LSB
S
ERIAL
M
ODE
T
IMING
T
ABLE
:
Interval
Symbol
A
B
C
Description
Parallel to Serial Setup Time
Serial Data Hold Time
LE delay from final serial clock rising edge
Min
Spec
100
10
10
Max
Spec
Units
nsec
nsec
nsec
Glitch-Free
TM
Digital Step Attenuator
4
Rev1 March 2012
IDTF1950
DATASHEET
7-bit 0.25 dB Digital Step Attenuator
150 MHz to 4000 MHz
P
ARALLEL
C
ONTROL
M
ODE
The user has the option of running in one of two parallel modes:
Direct Parallel Mode
or
Latched Parallel
Mode.
D
IRECT
P
ARALLEL
M
ODE
:
Direct Parallel Mode is selected when V
MODE
(pin 3) is < V
IL
and LE (pin 16) is > V
IH
. In this mode the
device will immediately react to any voltage changes to the parallel control pins [pins 19, 20, 21, 22, 23,
24, 1]. Use direct parallel mode for the fastest settling time.
L
ATCHED
P
ARALLEL
M
ODE
:
Latched Parallel Mode is selected when V
MODE
(pin 3) is < V
IL
and LE (pin 16) is toggled from < V
IL
to > V
IH
To utilize Latched Parallel Mode:
Set LE < V
IL
Adjust pins [19, 20, 21, 22, 23, 24, 1] to the desired attenuation setting. (Note the device will not
react to these pins while LE < V
IL
.)
Pull LE > V
IH
. The device will then transition to the attenuation settings reflected by these pins.
Latched Parallel Mode implies a default state for when the device is powered up with V
MODE
< V
IL
and LE < V
IL
.
In this case the default setting is MAXIMUM Attenuation.
L
ATCHED
P
ARALLEL
M
ODE
T
IMING
D
IAGRAM
:
(Note the Timing Spec Intervals in
Blue)
V
MODE
Spec
Intervals
A
D
C
B
Data Word
Latched into
Active Register
LE
D[6:0]
L
ATCHED
P
ARALLEL
M
ODE
T
IMING
T
ABLE
:
Interval
Symbol
A
B
C
D
Description
Serial to Parallel Mode Setup Time
Parallel Data Hold Time
LE minimum pulse width
Parallel Data Setup Time
Min
Spec
100
10
10
10
Max
Spec
Units
nsec
nsec
nsec
nsec
Glitch-Free
TM
Digital Step Attenuator
5
Rev1 March 2012
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