NCP81166, NCP81166A
Synchronous Buck MOSFET
Drivers
The NCP81166/A is a high performance dual MOSFET gate driver
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. 2mm x 2mm DFN8
package allows for space−optimized board layout.
Zero current detect feature allows for a high−efficiency solution
even at light load conditions. Pre−OVP feature aids in protecting the
load in the event of a short across the high−side FET. V
CC
UVLO
ensures the MOSFETs are off when supply voltages are low. A
bi−directional Enable pin provides a fault signal to the controller
when a pre−OVP or UVLO fault is detected.
Features
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1
DFN8
MN SUFFIX
CASE 506CN
•
•
•
•
•
•
•
•
•
•
•
•
Space−Efficient 2 mm x 2mm DFN8 Thermally−Enhanced Package
V
CC
Range of 4.5 V to 13.2 V
Integrated Bootstrap Diode
Pre−OVP Function Protects Load during HS FET Short
♦
NCP81166: 2.25 V SW Trip Threshold
♦
NCP81166A: 1.8 V SW Trip Threshold
Zero Current Detect Function Provides Power Saving Operation
during Light Load Conditions
Bi−directional Enable Feature pulls Enable pin low during pre−OVP
and UVLO Faults
5 V tri−state PWM Logic
Adaptive Anti−Cross−Conduction Circuit Protects against
Cross−Conduction during FET turn−on and turn−off
Output Disable Control turns off both MOSFETs via Enable pin
VCC Undervoltage Lockout
Direct interface to ASP1252, ASP1400 and other compatible PWM
Controllers
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAM
1
XXMG
G
XX = Specific Device Code
CE for NCP81166
CH for NCP81166A
M = Date Code
G
= Pb−Free Device
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
NCP81166MNTBG
NCP81166AMNTBG
Package
DFN8
(Pb−Free)
DFN8
(Pb−Free)
Shipping
†
3000 / Tape &
Reel
3000 / Tape &
Reel
Typical Applications
•
Power Solutions for Desktop Systems
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2015
1
January, 2015 − Rev. 2
Publication Order Number:
NCP81166/D
NCP81166, NCP81166A
PWM
NC
EN
VCC
(Top View)
Figure 1. Pin Diagram
1
GND
9
BST
DRVH
SW
DRVL
VCC
BST
DRVH
PWM
Logic
Anti−Cross
Conduction
VCC
DRVL
SW
EN
Fault
UVLO
Pre−OV
ZCD
Detection
Figure 2. Block Diagram
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
Symbol
PWM
NC
EN
VCC
DRVL
SW
DRVH
BST
GND
Description
Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode Emu-
lation Enabled, High = High Side FET Enabled.
No connect. There is no electrical connection from this pin to the die. Externally connecting this pin to ground
will not affect the functionality of the part.
Logic input. A logic high to enable the part and a logic low to disable the part. Pin is internally pulled low dur-
ing pre−OVP and UVLO faults.
Power supply input. Connect a bypass capacitor (1
mF)
from this pin to ground.
Low side gate drive output. Connect to the gate of low side MOSFET.
Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET.
High side gate drive output. Connect to the gate of high side MOSFET.
Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and
the SW pin.
Bias and reference ground. All signals are referenced to this node.
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NCP81166, NCP81166A
12V_POWER
TP1
R1
1.02
R164
C4
0.027uF
TP2
R142
VREG_SW1_HG
VREG_SW1_OUT
TP6
TP7
Q9
NTMFS4851N
Q10
NTMFS4851N
R3
2.2
JP13_ETCH
CSN11
C6
2700pF
JP14_ETCH
CSP11
0.0
TP5
L
235nH
VREG_SW1_LG
VCCP
0.0
R143 NCP81166/A
TP3
0.0
BST
HG
Q1
NTMFS4821N
C1
4.7uF
C2
4.7uF
C3
4.7uF
+
CE9
390uF
TP4
PWM
DRON
PWM SW
EN
VCC
PAD
C5
1uF
TP8
GND
LG
Figure 3. Application Circuit
Table 2. ABSOLUTE MAXIMUM RATINGS
Pin Symbol
VCC
BST
Pin Name
Main Supply Voltage Input
Bootstrap Supply Voltage
V
MAX
15 V
35 V wrt/ GND
40 V
≤
50 ns wrt/ GND
15 V wrt/ SW
35 V
40 V
≤
50 ns
BST+0.3 V
VCC+0.3 V
6.5 V
6.5 V
0V
V
MIN
−0.3 V
−0.3 V wrt/SW
SW
DRVH
DRVL
PWM
EN
GND
Switching Node
(Bootstrap Supply Return)
High Side Driver Output
Low Side Driver Output
DRVH and DRVL Control Input
Enable Pin
Ground
−5 V
−10 V (200 ns)
−0.3 V wrt/SW
−2 V (<200 ns) wrt/SW
−0.3 V DC
−5 V (<200 ns)
−0.3 V
−0.3 V
0V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. THERMAL INFORMATION
(All signals referenced to AGND unless noted otherwise)
Symbol
R
qJA
T
J
T
A
T
STG
MSL
Parameter
Thermal Characteristic (Note 1)
Operating Junction Temperature Range* (Note 2)
Operating Ambient Temperature Range*
Maximum Storage Temperature Range
Moisture Sensitivity Level
Value
74
−40 to 150
−10 to +125
−55 to +150
1
Unit
°C/W
°C
°C
°C
* The maximum package power dissipation must be observed.
1. I in
2
Cu, 1 oz thickness.
2. Operation at −40°C to −10°C guaranteed by design, not production tested.
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NCP81166, NCP81166A
Table 4. ELECTRICAL CHARACTERISTICS
(
Unless otherwise stated: −10°C < T
A
< +125°C; 4.5 V < V
CC
< 13.2 V,
4.5 V < BST−SWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V)
Parameter
SUPPLY VOLTAGE
VCC Operation Voltage
Pre−OVP Threshold
UNDERVOLTAGE LOCKOUT
VCC Start Threshold
VCC UVLO Hysteresis
Output Overvoltage Trip Threshold at
Startup
SUPPLY CURRENT
Normal Mode
Standby Current
Standby Current
Standby Current
BOOTSTRAP DIODE
Forward Voltage
PWM INPUT
PWM Input High
PWM Mid−State
PWM Input Low
ZCD Blanking Timer
HIGH SIDE DRIVER (VCC = 12 V)
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVH Rise Time tr
DRVH
DRVH Fall Time tf
DRVH
DRVH Turn−Off Propagation Delay
tpdl
DRVH
DRVH Turn−On Propagation Delay
tpdh
DRVH
SW Pull Down Resistance
DRVH Pull Down Resistance
HIGH SIDE DRIVER (VCC = 5 V)
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVH Rise Time tr
DRVH
DRVH Fall Time tf
DRVH
DRVH Turn−Off Propagation Delay
tpdl
DRVH
DRVH Turn−On Propagation Delay
tpdh
DRVH
SW Pull Down Resistance
VBST − VSW = 5 V
VBST − VSW = 5 V
V
VCC
= 5 V, 3 nF load, VBST − VSW = 5 V
V
VCC
= 5 V, 3 nF load, VBST − VSW = 5 V
C
LOAD
= 3 nF
C
LOAD
= 3 nF
SW to PGND
2.5
1.6
30
27
20
27
45
W
W
ns
ns
ns
ns
kW
VBST − VSW = 12 V
VBST − VSW = 12 V
V
VCC
= 12 V, 3 nF load, VBST−VSW = 12 V
V
VCC
= 12 V, 3 nF load, VBST−VSW = 12 V
C
LOAD
= 3 nF
C
LOAD
= 3 nF
SW to PGND
DRVH to SW, BST−SW = 0 V
45
45
8.0
1.9
1.0
16
11
3.0
1.7
30
25
30
30
W
W
ns
ns
ns
ns
kW
kW
250
3.4
1.3
2.7
0.7
V
V
V
ns
V
CC
= 12 V, forward bias current = 2 mA
0.1
0.4
0.6
V
Icc + Ibst, EN = 5 V, PWM = OSC, Fsw = 100 KHz,
Cload = 3 nF for DRVH, 3 nF for DRVL
Icc + Ibst, EN = GND
I
CC
+ I
BST
, EN = HIGH, PWM = LOW,
No loading on DRVH & DRVL
I
CC
+ I
BST
, EN = HIGH, PWM = HIGH,
No loading on DRVH & DRVL
10
0.5
2.0
2.0
1.4
mA
mA
mA
mA
VCC > Pre−OVP Threshold
NCP81166
NCP81166A
3.8
150
2.1
1.65
4.35
200
2.25
1.80
4.5
250
2.4
1.95
V
mV
V
4.5
2.75
13.2
3.2
V
V
Test Conditions
Min.
Typ.
Max.
Units
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NCP81166, NCP81166A
Table 4. ELECTRICAL CHARACTERISTICS
(
Unless otherwise stated: −10°C < T
A
< +125°C; 4.5 V < V
CC
< 13.2 V,
4.5 V < BST−SWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V)
Parameter
HIGH SIDE DRIVER (VCC = 5 V)
DRVH Pull Down Resistance
LOW SIDE DRIVER (VCC = 12 V)
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVL Rise Time tr
DRVL
DRVL Fall Time tf
DRVL
DRVL Turn−Off Propagation Delay
tpdl
DRVL
DRVL Turn−On Propagation Delay
tpdh
DRVL
DRVL Pull Down Resistance
LOW SIDE DRIVER (VCC = 5 V)
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVL Rise Time tr
DRVL
DRVL Fall Time tf
DRVL
DRVL Turn−Off Propagation Delay
tpdl
DRVL
DRVL Turn−On Propagation Delay
tpdh
DRVL
DRVL Pull Down Resistance
EN INPUT
Input Voltage High
Input Voltage Low
Hysteresis
Normal Mode Bias Current
Enable Pin Sink Current
Propagation Delay Time
SW Node
SW Node Leakage Current
Zero Cross Detection Threshold Voltage
SW to −20 mV, ramp slowly until BG goes off
(Start in DCM mode) (Note 3)
−6
20
mA
mV
−1
4
20
500
1
30
40
2.0
1.0
V
V
mV
mA
mA
ns
C
LOAD
= 3 nF
C
LOAD
= 3 nF
C
LOAD
= 3 nF
C
LOAD
= 3 nF
DRVL to PGND, VCC = PGND
2.5
1.0
30
22
27
12
45
W
W
ns
ns
ns
ns
kW
C
LOAD
= 3 nF
C
LOAD
= 3 nF
C
LOAD
= 3 nF
C
LOAD
= 3 nF
DRVL to PGND, VCC = PGND
8.0
45
2.0
0.7
16
11
3.0
1.5
35
20
35
30
W
W
ns
ns
ns
ns
kW
DRVH to SW, BST−SW = 0 V
45
kW
Test Conditions
Min.
Typ.
Max.
Units
Table 5. DECODER TRUTH TABLE
PWM INPUT
PWM High
PWM Mid
PWM Mid
PWM Low
3. Guaranteed by design; not production tested.
ZCD
ZCD Reset
Positive current through the inductor
Zero current through the inductor
ZCD Reset
DRVL
Low
High
Low
High
DRVH
High
Low
Low
Low
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