Advanced Power MOSFET
FEATURES
Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : 10
µA
(Max.) @ V
DS
= -200V
Low R
DS(ON)
: 0.581
Ω
(Typ.)
1
2
3
SFS9630
BV
DSS
= -200 V
R
DS(on)
= 0.8
Ω
I
D
= -4.4 A
TO-220F
1.Gate 2. Drain 3. Source
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J
, T
STG
T
L
Characteristic
Drain-to-Source Voltage
Continuous Drain Current (T
C
=25 C)
Continuous Drain Current (T
C
=100 C)
Drain Current-Pulsed
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (T
C
=25 C)
Linear Derating Factor
Operating Junction and
Storage Temperature Range
Maximum Lead Temp. for Soldering
Purposes, 1/8 “ from case for 5-seconds
o
2
O
1
O
1
O
3
O
o
o
Value
-200
-4.4
-3.3
1
O
Units
V
A
A
V
mJ
A
mJ
V/ns
W
W/ C
o
-18
+ 30
_
258
-4.4
3.3
-5.0
33
0.26
- 55 to +150
o
C
300
Thermal Resistance
Symbol
R
θ
JC
R
θ
JA
Characteristic
Junction-to-Case
Junction-to-Ambient
Typ.
--
--
Max.
3.79
62.5
Units
o
C/W
Rev. B
©1999 Fairchild Semiconductor Corporation
SFS9630
Symbol
BV
DSS
∆BV/∆T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Characteristic
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
Gate-Source Leakage , Forward
Gate-Source Leakage , Reverse
Drain-to-Source Leakage Current
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain( “ Miller “ ) Charge
Min. Typ. Max. Units
-200
--
-2.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-0.17
--
--
--
--
--
--
3.7
740
125
49
14
22
41
17
29
5.8
13.6
--
--
-4.0
-100
100
-10
-100
0.8
--
965
185
75
35
55
90
45
36
--
--
nC
ns
pF
µA
Ω
Ω
V
o
P-CHANNEL
POWER MOSFET
Electrical Characteristics
(T
C
=25
o
C unless otherwise specified)
Test Condition
V
GS
=0V,I
D
=-250µA
See Fig 7
V
DS
=-5V,I
D
=-250µA
V
GS
=-30V
V
GS
=30V
V
DS
=-200V
V
DS
=-160V,T
C
=125 C
V
GS
=-10V,I
D
=-2.2A
V
DS
=-40V,I
D
=-2.2A
4
O
4
O
o
V/ C I
D
=-250µA
V
nA
V
GS
=0V,V
DS
=-25V,f =1MHz
See Fig 5
V
DD
=-100V,I
D
=-6.5A,
R
G
=12Ω
See Fig 13
4
5
OO
V
DS
=-160V,V
GS
=-10V,
I
D
=-6.5A
See Fig 6 & Fig 12
4
5
OO
Source-Drain Diode Ratings and Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
Characteristic
Continuous Source Current
Pulsed-Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
1
O
4
O
Min. Typ. Max. Units
--
--
--
--
--
--
--
--
160
0.96
-4.4
-18
-5.0
--
--
A
V
ns
µC
Test Condition
Integral reverse pn-diode
in the MOSFET
T
J
=25 C,I
S
=-4.4A,V
GS
=0V
T
J
=25 C,I
F
=-6.5A
di
F
/dt=100A/µs
4
O
o
o
Notes ;
1 Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
O
2
O
L=20mH, I
AS
=-4.4A, V
DD
=-50V, R
G
=27Ω
*
, Starting T
J
=25
o
C
_
3
_
<
O
I
SD
<
-6.5A,
di/dt
<
400A/µs, V
DD
_
BV
DSS
, Starting T
J
=25
o
C
4
<
O
Pulse Test : Pulse Width = 250
µs,
Duty Cycle
_
2%
5
O
Essentially Independent of Operating Temperature
P-CHANNEL
POWER MOSFET
Fig 1. Output Characteristics
V
GS
SFS9630
Fig 2. Transfer Characteristics
[A]
-I
D
, Drain Current
[A]
10
1
-I
D
, Drain Current
- 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom : - 4.5 V
Top :
10
1
10
0
10
0
150
o
C
25
o
C
@ Notes :
1. V = 0 V
GS
2. V = -40 V
DS
- 55 C
o
@ Notes :
1. 250
µ
s Pulse Test
2. T = 25
o
C
C
10
-1
10
-1
0
10
3. 250
µ
s Pulse Test
10
1
10
-1
2
4
6
8
10
-V
DS
, Drain-Source Voltage [V]
-V
GS
, Gate-Source Voltage [V]
R
DS(on)
, [ ]
Ω
Drain-Source On-Resistance
Fig 3. On-Resistance vs. Drain Current
2.5
[A]
Fig 4. Source-Drain Diode Forward Voltage
-I
DR
, Reverse Drain Current
2.0
10
1
1.5
V = -10 V
GS
1.0
10
0
150
o
C
25
o
C
@ Notes :
1. V = 0 V
GS
2. 250
µ
s Pulse Test
0.5
V
GS
= -20 V
0.0
0
4
8
12
16
20
24
@ Note : T = 25
o
C
J
10
-1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-I
D
, Drain Current [A]
-V
SD
, Source-Drain Voltage [V]
Fig 5. Capacitance vs. Drain-Source Voltage
C = C + C ( C
ds
= shorted )
iss gs gd
C =C +C
oss ds gd
Fig 6. Gate Charge vs. Gate-Source Voltage
[V]
1500
[pF]
C
iss
1000
C =C
rss gd
-V
GS
, Gate-Source Voltage
10
V
DS
= -40 V
V
DS
= -100 V
V
DS
= -160 V
Capacitance
C
oss
@ Notes :
1. V = 0 V
GS
2. f = 1 MHz
5
500
C
rss
@ Notes : I =-6.5 A
D
0
0
5
10
15
20
25
30
0
0
10
1
10
-V
DS
, Drain-Source Voltage [V]
Q
G
, Total Gate Charge [nC]
SFS9630
Drain-Source Breakdown Voltage
P-CHANNEL
POWER MOSFET
Fig 8. On-Resistance vs. Temperature
Drain-Source On-Resistance
3.0
Fig 7. Breakdown Voltage vs. Temperature
1.2
-BV , (Normalized)
DSS
R
DS(on)
, (Normalized)
2.5
1.1
2.0
1.0
1.5
1.0
@ Notes :
1. V = -10 V
GS
2. I = -3.3 A
D
0.9
@ Notes :
1. V = 0 V
GS
2. I = -250
µ
A
D
0.5
0.8
-75
-50
-25
0
25
50
75
100
125
150
175
0.0
-75
-50
-25
0
25
50
75
100
125
150
175
T
J
, Junction Temperature [
o
C]
T
J
, Junction Temperature [
o
C]
Fig 9. Max. Safe Operating Area
[A]
10
2
Operation in This Area
is Limited by R
DS(on)
Fig 10. Max. Drain Current vs. Case Temperature
6
-I
D
, Drain Current
[A]
5
10
1
-I
D
, Drain Current
0.1 ms
1 ms
10 ms
4
3
10
0
DC
@ Notes :
1. T = 25
o
C
C
2. T =
J
3. Single Pulse
150
o
C
2
1
10
-1
10
0
10
1
10
2
0
25
50
75
100
o
125
150
-V
DS
, Drain-Source Voltage [V]
T
c
, Case Temperature [ C]
Fig 11. Thermal Response
Thermal Response
D=0.5
10
0
0.2
0.1
0.05
0.02
10
- 1
0.01
single pulse
@ Notes :
1. Z
θ
J C
(t)=3.79
Max.
2. Duty Factor, D=t
1
/t
2
3. T
J M
-T
C
=P
D M
*Z
θ
J C
(t)
o
C/W
P
.
DM
t
1.
t
2.
Z
θ
JC
(t) ,
10
- 5
10
- 4
10
- 3
10
- 2
10
- 1
10
0
10
1
t
1
, Square Wave Pulse Duration
[sec]
P-CHANNEL
POWER MOSFET
Fig 12. Gate Charge Test Circuit & Waveform
SFS9630
“ Current Regulator ”
50KΩ
12V
200nF
300nF
Same Type
as DUT
V
GS
Q
g
-10V
V
DS
V
GS
DUT
-3mA
Q
gs
Q
gd
R
1
Current Sampling (I
G
)
Resistor
R
2
Current Sampling (I
D
)
Resistor
Charge
Fig 13. Resistive Switching Test Circuit & Waveforms
R
L
V
out
V
in
R
G
DUT
-10V
V
out
90%
t
on
t
off
t
r
t
d(off)
t
f
V
DD
( 0.5 rated V
DS
)
t
d(on)
V
in
10%
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
L
L
V
DS
Vary t
p
to obtain
required peak I
D
BV
DSS
1
2
--------------------
E
AS
= ---- L
L
I
AS
2
BV
DSS
-- V
DD
t
p
I
D
V
DD
Time
V
DS
(t)
R
G
DUT
-10V
t
p
C
V
DD
I
D
(t)
I
AS
BV
DSS
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