EM47EM1688SBB
4Gb (32M×8Bank×16) Double DATA RATE 3 SDRAM
Features
• JEDEC Standard VDD/VDDQ = 1.5V±0.075V.
• All inputs and outputs are compatible with SSTL_15
interface.
• Fully differential clock inputs (CK, /CK) operation.
• Eight Banks
• Posted CAS by programmable additive latency
• Bust length: 4 with Burst Chop (BC) and 8.
• CAS Write Latency (CWL): 5,6,7,8
• CAS Latency (CL): 6,7,8,9,10,11
• Write Latency (WL) =Read Latency (RL) -1.
• Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
• On chip DLL align DQ, DQS and /DQS transition
with CK transition.
• DM mask write data-in at the both rising and falling
edges of the data strobe.
• Sequential & Interleaved Burst type available both
for 8 & 4 with BC.
• Multi Purpose Register (MPR) for pre-defined
pattern read out
• On Die Termination (ODT) options: Synchronous
ODT, Dynamic ODT, and Asynchronous ODT
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
• RoHS Compliance
• Driver Strength:RZQ/7, RZQ/6 (RZQ=240Ω)
• High Temperature Self-Refresh rate enable
• ZQ calibration for DQ drive and ODT
• RESET pin for initialization and reset function
Description
The EM47EM1688SBB is a high speed Double Date
Rate 3 (DDR3) Synchronous DRAM fabricated with
ultra high performance CMOS process containing 4G
bits which organized as 32Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed
double-data-rate transfer rates of up to 1600
Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key
DDR3 SDRAM features: (1) posted CAS with
additive latency, (2) write latency = read latency -1,
(3) On Die Termination (4) programmable driver
strength data,(5) seamless BL4 access. All of the
control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs
are latched at the cross point of differential clocks
(CK rising and /CK falling). All I/Os are synchronized
with a pair of bidirectional differential data strobes
(DQS and /DQS) in a source synchronous fashion.
The address bus is used to convey row, column and
bank address information in a /RAS and /CAS
multiplexing style. The 4Gb DDR3 devices operates
with a single power supply: 1.5V ± 0.075V VDD and
VDDQ. Available package: FBGA-96Ball (with 0.8mm
x 0.8mm ball pitch)
Oct. 2013
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EM47EM1688SBB
Pin Description (Simplified)
Pin
Name
Function
(System Clock)
J7,K7
CK, /CK
CK and CK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of
CK and negative edge of CK . Output (read) data is referenced to
the crossings of CK and /CK (both directions of crossing).
(Chip Select)
L2
All commands are masked when /CS is registered HIGH.
/CS
/CS provides for external Rank selection on systems with
multiple Ranks. /CS is considered part of the command code.
(Clock Enable)
CKE high activates and CKE low deactivates internal clock
signals and device input buffers and output drivers. Taking CKE
low provides precharge power-down and self- refresh operation
(all banks idle), or active power-down (row active in any bank).
CKE is asynchronous for self refresh exit. After VREFCA has
become stable during the power on and initialization sequence, it
must be maintained during all operations (including self-refresh).
CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, /CK , ODT and CKE are
disabled during power-down. Input buffers, excluding CKE, are
disabled during self -refresh.
(Address)
Provided the row address (RA0 – RA14) for active commands
and the column address (CA0-CA9) and auto precharge bit for
read/write commands to select one location out of the memory
array in the respective bank. A10 is sampled during a precharge
command to determine whether the precharge applies to one
bank (A10 LOW) or all banks (A10 HIGH). The address inputs
also provide the op-code during Mode Register Set commands.
A12 is sampled during read and write commands to determine if
burst chop (on-the-fly) will be performed. (HIGH: no burst chop,
LOW: burst chopped). See command truth table for details.
(Bank Address)
M2,N8,M3
BA0, BA1,BA2
BA0 – BA2 define to which bank an active, read, write or
precharge command is being applied. Bank address also
determines if the mode register is to be accessed during a MRS
cycle.
(On Die Termination)
ODT (registered HIGH) enables termination resistance internal to
the DDR3 SDRAM. When enabled, ODT is applied to each DQ,
DQS, DQS , DMU and DML signal. The ODT pin will be ignored if
the Mode Register
MR1
is programmed to disable ODT.
K9
CKE
N3,P7,P3,N2,
P8,P2,R8,R2,
T8,R3,L7,R7,
N7,T3,T7
A0~A9,A10/AP,
A11,A12( /BC ),
A13,A14
K1
ODT
Oct. 2013
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