EM47FM3288SBB_15 datasheet, PDF

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EM47FM3288SBB_15: DescriptionDouble DATA RATE 3 Stack SDRAM; File Size1MB，41 Pages; ManufacturerEOREX; Websitehttp://www.eorex.com

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EM47FM3288SBB_15 Overview

Double DATA RATE 3 Stack SDRAM

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EM47FM3288SBB

16Gb (64M×8Bank×32) Double DATA RATE 3 Stack SDRAM

Features

• JEDEC Standard VDD/VDDQ = 1.5V 0.075V.

• All inputs and outputs are compatible with SSTL_15

interface.

• Fully differential clock inputs (CK, /CK) operation.

• Eight Banks

• Posted CAS by programmable additive latency

• Bust length: 4 with Burst Chop (BC) and 8.

• CAS Write Latency (CWL): 5,6,7,8

• CAS Latency (CL): 6,7,8,9,10,11

• Write Latency (WL) =Read Latency (RL) -1.

• Bi-directional Differential Data Strobe (DQS).

• Data inputs on DQS centers when write.

• Data outputs on DQS, /DQS edges when read.

• On chip DLL align DQ, DQS and /DQS transition

with CK transition.

• DM mask write data-in at the both rising and falling

edges of the data strobe.

• Sequential & Interleaved Burst type available both

for 8 & 4 with BC.

• Multi Purpose Register (MPR) for pre-defined

pattern read out

• On Die Termination (ODT) options: Synchronous

ODT, Dynamic ODT, and Asynchronous ODT

• Auto Refresh and Self Refresh

• 8,192 Refresh Cycles / 64ms

• Refresh Interval: 7.8us T

case

between 0 C ~ 85 C

• Refresh Interval: 3.9us T

case

between 85 C ~ 95 C

• RoHS Compliance

• Driver Strength:RZQ/7, RZQ/6 (RZQ=240 )

• High Temperature Self-Refresh rate enable

• ZQ calibration for DQ drive and ODT

• RESET pin for initialization and reset function

Description

The EM47FM3288SBA is a high speed stack

multi-chip package integrated 4Gbits x4 DDR3

SDRAM and fabricated with ultra high performance

CMOS process containing 16G bits which organized

as 64Mbits x 8 banks by 32 bits. This synchronous

device achieves high speed double-data-rate transfer

rates of up to 1600 Mb/sec/pin (DDR3-1600) for

general applications. The chip is designed to comply

with the following key DDR3 SDRAM features: (1)

posted CAS with additive latency, (2) write latency =

read latency -1, (3) On Die Termination (4)

programmable driver strength data,(5) seamless BL4

access. All of the control and address inputs are

synchronized with a pair of externally supplied

differential clocks. Inputs are latched at the cross

point of differential clocks (CK rising and /CK falling).

All I/Os are synchronized with a pair of bidirectional

differential data strobes (DQS and /DQS) in a source

synchronous fashion. The address bus is used to

convey row, column and bank address information in

a /RAS and /CAS multiplexing style. The 16Gb DDR3

devices operates with a single power supply: 1.5V ±

0.075V VDD and VDDQ. Available package with

RoHS compliance: FBGA-136Ball (14 x 12 x 1.4

mm )

Jul. 2012

1/41

www.eorex.com

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