ES I G
TM
EW D N T
RN
D F O LA C EM E
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NDE
P
MME DED RE eb. 2004
CO
Data
N
RE
E
Sheet
le F
NOT ECOMM (Availab
R
232
I S L6
NS
IPM6220
December 2000
FN4903.1
Advanced Triple PWM and Dual Linear
Power Controller for Portable
Applications
The IPM6220 provides a highly integrated power control and
protection solution for five output voltages required in high-
performance notebook PC applications. The IC integrates
three fixed frequency pulse-width-modulation (PWM)
controllers and two linear regulators along with monitoring and
protection circuitry into a single 24 lead SSOP package.
The two PWM controllers that regulate the system main 5V
and 3.3V voltages are implemented with synchronous-
rectified buck converters. Synchronous rectification and
hysteretic operation at light loads contribute to high efficiency
over a wide range of input voltage and load variation.
Efficiency is further enhanced by using the lower MOSFET’s
r
DS(ON)
as the current sense element. Input voltage feed-
forward ramp modulation, current-mode control, and internal
feed-back compensation provide fast and stable handling of
input voltage load transients encountered in advanced
portable computer chip sets.
The third PWM controller is a boost converter that regulates a
resistor selectable output voltage of nominally 12V.
Two internal linear regulators provide +5V ALWAYS and
+3.3V ALWAYS low current outputs required by the notebook
system controller.
Features
• Provides Five Regulated Voltages
- +5V ALWAYS
- +3.3V ALWAYS
- +5V Main
- +3.3V Main
- +12V
• High Efficiency Over Wide Line and Load Range
- Synchronous Buck Converters on Main Outputs
- Hysteretic Operation at Light Load
• No Current-Sense Resistor Required
- Uses MOSFET’s r
DS(ON)
- Optional Current-Sense Resistor for More Precision
• Operates Directly From Battery 5.6 to 22V Input
• Input Undervoltage Lock-Out (UVLO)
• Excellent Dynamic Response
- Voltage Feed-Forward and Current-Mode Control
• Monitors Output Voltages
• Synchronous Converters Operate Out of Phase
• Separate Shut-Down Pins for Advanced Configuration and
Power Interface (ACPI) Compatibility
• 300kHz Fixed Switching Frequency on Main Outputs
• Thermal Shut-Down Protection
Ordering Information
PART NUMBER
IPM6220CA
IPM6220EVAL1
TEMP.
RANGE (
o
C)
0 to 70
PACKAGE
24 Ld SSOP
PKG.
NO.
M24.15
Applications
• Mobile PCs
• Hand-Held Portable Instruments
Evaluation Board
Pinout
IPM6220 (SSOP)
TOP VIEW
VBATT 1
3.3V ALWAYS 2
BOOT2 3
UGATE2 4
PHASE2 5
5V ALWAYS 6
LGATE2 7
PGND2 8
ISEN2 9
VSEN2 10
SDWN2 11
PGOOD 12
24 BOOT1
23 UGATE1
22 PHASE1
21 ISEN1
20 LGATE1
19 PGND1
18 VSEN1
17 SDWN1
16 GATE3
15 VSEN3
14 GND
13 SDWNALL
Related Literature
• Application Note AN9915
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright © Intersil Corporation 2000
Block Diagram
VBATT
GND
UVFLT
GATE LOGIC 1
HGDR1
UGATE1
PHASE1
HI
CLK
200ns
RAMP 1
PWMMD1
POWER-ON
RESET (POR)
POR
DEADTIME
VCC
LGDR1
LO
OVP1
HYST COMP1
-
+
OC COMP1
PWM VCC
LATCH 1
OC LOGIC1
+
-
+
EA1
-
-
+
REF
-
+
∑
VOLT-
SECOND
CLAMP
PWMMD1
CLK1
PGND1
VSEN1
LGATE1
PWM/HYST
PWM ON
HYST ON
CLK1
SHUTOFF
BOOT1
VSEN3
GATE3
CLK1
BOOST
CONTROLLER
RAMP 2
CLK2
+
2.8V
+
EA2
+
-
D Q
R
> Q
VOLT-
SECOND
CLAMP
∑
-
+
SDWN
REF
+
ISEN2
+
PWM MODE 2 -
PWMMD2
R1 = 20K
-
UVFLT
OVP1
OVP2
OUTPUT
VOLTAGE
MONITOR
PGOOD
LDO2
+
LGATE2
LGATE2
-
2
Q D
R
Q <
R1 = 20K
-
+
VBATT
VSEN1
LGATE1
OC
LOGIC2
VCC PWM
LATCH 2
POR
LDO1
REFERENCE
VCC
SDWN
AND
SOFT START
REF
3.3V-ALWAYS
5V-ALWAYS
2.5V
REF
BOOT2
UGATE2
HGDR2
GATE LOGIC 2
HI
PHASE2
PWMMD2
SHUTOFF
VCC
DEADTIME
PWM/HYST
LGATE2
LGDR2
LO
PWM ON
PGND2
OVP2
HYST ON
IPM6220
VSEN2
HYST COMP2
CLK2
-
+
- PWM MODE 1
ISEN1
OC COMP2
-
LGATE1
SDWN1
SDWN2
SDWNALL
FIGURE 1.
IPM6220
Simplified Power System Diagram
VBATT
VBATT
Q1
3.3V ALWAYS
LINEAR
CONTROLLER
LINEAR
CONTROLLER
5V MAIN
PWM1
CONTROLLER
Q2
5V ALWAYS
IPM6220
VBATT
Q1
3.3V MAIN
PWM2
CONTROLLER
Q2
VOLTAGE,
CURRENT
MONITORS
PGOOD
12V BOOST
PWM3
CONTROLLER
FIGURE 2.
Typical Application
+V
BATT
PROCESSOR
SDWN1
SDWN2
5V MAIN
3.3V MAIN
5V ALWAYS
3.3V ALWAYS
12V
PCM
CIA
ENABLE
C8051
VID CODE
SDWN
V
I/O
I/O
CLOCK
RESET
V
CORE
µP
CORE
IPM6220
IPM6210
V
CLOCK
PGOOD
PGOOD
SDWNALL
ON/OFF
FIGURE 3.
3
IPM6220
I
Absolute Maximum Ratings
Input Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +29.0V
Phase, ISEN and SDWNALL Pins . . . . . . . . . . . GND -0.3V to +29.0V
Boot and UGATE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +29.0V
BOOT1, 2 with Respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . . +6.5V
All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
SSOP Package . . . . . . . . . . . . . . . . . .
88
28.5
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SSOP - Lead Tips Only)
Operating Conditions
Input Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . +5.6V to +22.0V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0
o
C to 125
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
Input Quiescent Current
Stand-by Current
Shut-down Current
Input Under-voltage Lock Out
Input Under-voltage Lock Out
OSCILLATOR
PWM1,2 Oscillator Frequency
REFERENCE AND SOFT START
Internal Reference Voltage
Reference Voltage Accuracy
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic
SYMBOL
I
CC
I
CCSB
I
CCSN
UVLO
UVLO
TEST CONDITIONS
SDWN1
=
SDWN2 = 5V, SDWNALL = VIN,
Outputs open circuited
SDWN1
=
SDWN2 = 0V, SDWNALL = VIN,
Outputs open circuited
SDWNALL = 0V
Rising VBATT
VBATT, Hysteresis
MIN
-
-
-
4.3
TYP
1.4
300
<1.0
4.7
150
5.1
MAX
2.0
UNITS
mA
µA
µA
V
mV
F
c1,2
255
300
345
kHz
V
REF
-
-1.0
2.472
-
5
-
+1.0
-
V
%
µA
SDWN1, SDWN2 Output Current During
Start-up
PWM1 CONVERTER, 5V Main
Output Voltage
Line and Load Regulation
Under-Voltage Shut-Down Level
Current Limit Threshold
Over-Voltage Threshold
Maximum Duty Cycle
PWM2 CONVERTER, 3.3V Main
Output Voltage
Line and Load Regulation
Under-Voltage Shut-Down Level
Current Limit Threshold
Over-Voltage Threshold
Maximum Duty Cycle
I
SS
-
V
OUT1
0.0 < IVOUT1 < 5.0A; 5.6V < VBATT < 22.0V
V
UV1
I
OC2
V
OVP1
DC
MAX
2µs delay, % Feedback Voltage at VSNS1 pin
Current from ISNS1 Pin Through RSNS1
2µs delay, % Feedback Voltage at VSNS1 pin
SDWN1 > 4.0V
-2
70
90
110
5.0
0.5
75
135
115
94
+2
80
180
120
V
%
%
µA
%
%
VOUT2
0.0 < IVOUT2 < 5.0A; 5.6V < VBATT < 24.0V
V
UV2
I
OC2
V
OVP2
DC
MAX
2µs delay, % Feedback Voltage at VSNS2 pin
Current from ISNS2 Pin Through RSNS2
2µs delay, % Feedback Voltage at VSNS2 pin
SDWN2 > 4.0V
-2
70
90
110
3.3
0.5
75
135
115
94
+2
80
180
120
V
%
%
µA
%
%
4
IPM6220
Electrical Specifications
PARAMETER
Internal Resistance to GND on VSNS2 Pin
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic
(Continued)
SYMBOL
R
VSNS2
TEST CONDITIONS
MIN
TYP
66K
MAX
UNITS
Ω
PWM1 and PWM2 CONTROLLER GATE DRIVERS
Upper Drive Pull-Up Resistance
Upper Drive Pull-Down Resistance
Lower Drive Pull-Up Resistance
Lower Drive Pull-Down Resistance
PWM 3 CONVERTER
12V Feedback Regulation Voltage
12V Feedback Regulation Voltage Input
Current
Line and Load Regulation
Under-Voltage Shut-Down Level
Over-Voltage Threshold
PWM3 Oscillator Frequency
Maximum Duty Cycle
PWM 3 CONTROLLER GATE DRIVERS
Pull-Up Resistance
Pull-Down Resistance
5V and 3.3V ALWAYS
Linear Regulator Accuracy
5V ALWAYS Output Voltage Regulation
Maximum Output Current
Current Limit
5V ALWAYS Under-Voltage Shut-Down
Bypass Switch rDS(ON)
POWER GOOD AND CONTROL FUNCTIONS
Power Good Threshold for PWM1 and
PWM2 Output Voltages
PGOOD Leakage Current
PGOOD Voltage Low
PGOOD Minimum Pulse Width
SDWN1, 2, - Low (Off)
SDWN1, 2, - High (On)
SDWNALL - High (On)
SDWNALL - Low (Off)
Over-Temperature Shutdown
Over-Temperature Hysteresis
SDWNALL, Hysteresis
I
PGLKG
V
PGOOD
T
PGmin
VPULLUP = 5.0V
I
PGOOD
= -4mA
-14
-
-12
-
0.2
10
0.8
4.3
2.4
40
150
25
-10
1.0
0.5
%
µA
V
µs
V
V
V
mV
o
C
o
C
R
2UGPUP
R
2UGPDN
R
2LGPUP
R
2LGPDN
-
-
-
-
7
4
6
5
12
10
9
8
Ω
Ω
Ω
Ω
VSEN3
I
VSEN3
0.0 < IV
OUT3
< 120mA, 4.9V< 5VMain <5.1V
V
UV3
V
OVP3
F
c3
2µs delay, % Feedback Voltage at VSNS3 pin
2µs delay, % Feedback Voltage at VSNS3 pin
85
-2
70
2.472
0.1
1.0
+2
75
115
100
33
80
120
115
V
µA
%
%
%
kHz
%
R3GPUP
R3GPDN
6
6
12
12
Ω
Ω
PWM1, 5V Output OFF (SDWN1 = 0V);
5.6V < VBATT < 22V; 0 < I
LOAD
< 50mA
PWM1, 5V Output ON (SDWN1 = 5V);
0 < I
LOAD
< 50mA
Combined 5V ALWAYS and 3.3V ALWAYS
Combined 5V ALWAYS and 3.3V ALWAYS
-2.0
-3.3
50
100
0.5
1.0
+2.0
+2.0
%
%
mA
180
75
mA
%
Ω
PWM1, 5V Output ON (SDWN1 = 5V)
1.3
5
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