MMDF4P03HD
Preferred Device
Power MOSFET
4 A, 30 V, P−Channel SO−8, Dual
Dual MOSFET devices are designed for use in low voltage, high
speed switching applications where power efficiency is important.
Typical applications are dc−dc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives.
•
Low R
DS(on)
Provides Higher Efficiency and Extends Battery Life
•
Logic Level Gate Drive
−
Can Be Driven by Logic ICs
•
Miniature SO−8 Surface Mount Package
−
Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, With Soft Recovery
•
I
DSS
Specified at Elevated Temperature
•
Mounting Information for SO−8 Package Provided
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
−
Continuous
Drain Current
−
Continuous @ T
A
= 25°C
Drain Current
−
Single Pulse (t
p
≤
10
ms)
Source Current
−
Continuous @ T
A
= 25°C
Total Power Dissipation @ T
A
= 25°C
(Note 1)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy
−
Starting T
J
= 25°C
(V
DD
= 30 Vdc, V
GS
= 5.0 Vdc,
V
DS
= 20 Vdc, I
L
= 9.0 Apk,
L = 10 mH, R
G
= 25
W)
Thermal Resistance
−
Junction−to−Ambient
Maximum Lead Temperature for Soldering
Purposes, (1/8″ from Case for 10 s)
Symbol
V
DSS
V
GS
I
DM
I
S
P
D
T
J
, T
stg
E
AS
I
D
Value
30
±
20
4.0
20
1.7
2.0
−
55 to
150
450
Unit
Vdc
Vdc
Adc
Apk
Adc
Watts
°C
mJ
8
1
SO−8, Dual
CASE 751
STYLE 11
A
Y
WW
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4 AMPERES
30 VOLTS
R
DS(on)
= 85 mW
P−Channel
D
D
G
S
G
S
MARKING
DIAGRAM
8
DP0303
AYWW
1
= Assembly Location
= Year
= Work Week
PIN ASSIGNMENT
R
θJA
T
L
62.5
260
°C/W
°C
Source−1
Gate−1
Source−2
Gate−2
1
2
3
4
8
7
6
5
Drain−1
Drain−1
Drain−2
Drain−2
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1 Mounted on G10/FR4 glass epoxy board using minimum recommended
footprint.
Top View
ORDERING INFORMATION
Device
MMDF4P03HDR2
Package
SO−8
Shipping
†
2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 3
1
Publication Order Number:
MMDF4P03HD/D
MMDF4P03HD
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Zero Gate Voltage Drain Current
(V
DS
= 24 Vdc, V
GS
= 0 Vdc)
(V
DS
= 24 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±20
Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 3.5 Adc)
(V
GS
= 4.5 Vdc, I
D
= 2.0 Adc)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 3.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(V
DD
= 15 Vdc,
V
GS
= 10 Vdc,
I
D
= 1.0 Adc,
R
G
= 6.0
Ω)
t
d(on)
t
r
t
d(off)
t
f
Q
T
(V
DS
= 10 Vdc,
I
D
= 3.5 Adc,
V
GS
= 10 Vdc)
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 1.7 Adc, V
GS
= 0 Vdc)
(I
S
= 1.7 Adc, V
GS
= 0 Vdc,
T
J
= 125°C)
(I
S
= 3.5 Adc,
V
GS
= 0 Vdc,
dI
S
/dt = 100 A/μs)
Reverse Recovery Stored Charge
2. Pulse Test: Pulse Width
≤
300
μs,
Duty Cycle
≤
2%.
3. Switching characteristics are independent of operating junction temperature.
V
SD
Vdc
−
−
−
−
−
−
0.9
0.7
77.4
19.9
57.5
0.088
1.2
−
−
−
−
−
μC
ns
−
−
−
−
−
−
−
−
11.7
15.8
167.3
102.6
14.8
1.7
4.7
3.42
23.4
31.6
334.6
205.2
29.6
−
−
−
nC
ns
(V
DS
= 24 Vdc,
V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
425
209
57.2
600
300
80
pF
V
GS(th)
Vdc
1.0
−
−
Ω
V
(BR)DSS
I
DSS
Vdc
30
−
−
−
−
−
−
−
−
1.0
20
100
μAdc
Symbol
Min
Typ
Max
Unit
I
GSS
nAdc
R
DS(on)
−
−
−
0.075
0.125
6.0
0.085
0.16
−
g
FS
Mhos
Reverse Recovery Time
t
rr
t
a
t
b
Q
RR
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2
MMDF4P03HD
TYPICAL ELECTRICAL CHARACTERISTICS
6.0
5.0
4.0
3.0
2.0
1.0
0
6.0
5.0
4.0
3.0
2.0
1.0
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
25°C
T
J
= −55°C
V
DS
≥
10 V
100°C
V
GS
= 10 V
6.0 V
4.5 V
4.3 V
4.1 V
3.9 V
T
J
= 25°C
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
3.7 V
3.5 V
3.3 V
3.1 V
2.9 V
2.7 V
Figure 1. On−Region Characteristics
R DS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
T
J
= 25°C
I
D
= 3 A
R DS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
1.0
1.5
Figure 2. Transfer Characteristics
T
J
= 25°C
V
GS
= 4.5 V
10 V
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
I
D
, DRAIN CURRENT (AMPS)
R DS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
Figure 3. On−Resistance versus
Gate−To−Source Voltage
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
−50
1.0
−25
0
25
50
75
100
125
150
0
V
GS
= 10 V
I
D
= 1.5 A
IDSS , LEAKAGE (nA)
100
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
V
GS
= 0 V
T
J
= 125°C
10
100°C
5.0
10
15
20
25
30
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MMDF4P03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
1000
T
J
= 25°C
800
C, CAPACITANCE (pF)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
600
C
iss
400
C
oss
200
C
rss
0
−10
−5.0
V
GS
0
V
DS
5.0
10
15
20
25
30
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
MMDF4P03HD
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
7.0
QT
6.0
V
GS
5.0
4.0
3.0
2.0
1.0
Q3
0
0
2.0
4.0
6.0
8.0
10
V
DS
12
14
0
16
I
D
= 3 A
T
J
= 25°C
10
Q1
Q2
20
30
1000
V
DD
= 15 V
I
D
= 3 A
V
GS
= 10 V
T
J
= 25°C t
d(off)
t
f
V DS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
t, TIME (ns)
t
r
10
t
d(on)
1.0
1.0
10
R
G
, GATE RESISTANCE (OHMS)
100
Q
g
, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
rr
, due
to the storage of minority carrier charge, Q
RR
, as shown in
the typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t
rr
and low Q
RR
specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
2.5
V
GS
= 0 V
T
J
= 25°C
2.0
high di/dts. The diode’s negative di/dt during t
a
is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during t
b
is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
b
/t
a
serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
rr
), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
IS , SOURCE CURRENT (AMPS)
1.5
1.0
0.5
0
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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Embedded System
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