User's Guide
SNVU302 – March 2014
LM46002EVM User’s Guide
Introduction
The Texas Instruments LM46002EVM evaluation module (EVM) helps designers evaluate the operation
and performance of the LM46002 wide-input voltage Simple Switcher
®
buck regulator. The device offers
configurability in a 1-V to 28-V output voltage, synchronous rectification and a 200-kHz to 2.2-MHz
adjustable frequency range. It also offers external frequency synchronization, power good (PG) flag, and a
precision enable to program undervoltage lockout (UVLO) and internal compensation. The LM46002EVM
is configured for an output voltage of 3.3 V and a switching frequency of 500 kHz. Refer to the LM46002
datasheet for additional features, detailed description and available options.
The EVM contains one DC-DC converter (See
Table 1).
Table 1. Device and Package Configurations
CONVERTER
U1
IC
LM46002
PACKAGE
(PWP) HTSSOP-16
Setup
This section describes the test points and connectors on the EVM and how to properly connect, set up
and use the LM46002EVM. Please refer to
Figure 1
for a top view of the EVM and relative placement of
the different test points and edge connector.
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Input/Output (I/O) Connector Description
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Figure 1. Top View of LM46002EVM
1
Input/Output (I/O) Connector Description
VIN – Terminal on J2—
is the power input terminal for the converter. The terminal edge connector also
provides a power (VIN) and ground (GND) connection to allow the user to attach the EVM to a
cable harness.
VOUT – Terminal on J3—
is the regulated output voltage for the converter. The terminal edge connector
also provides a power (VOUT) and ground (GND) connection to allow the user to attach the EVM to
a cable harness.
GND – Terminal on J2 and J3—
are the ground reference for the converter. The terminal edge connector
also provides a GND connection for attaching the EVM to a cable harness.
EN – Testpoint—
is used to enable the converter by supplying a voltage greater than 2.2 V (typ) or just to
monitor the voltage on this terminal whenever a resistor divider is in place (for precision enable
applications). The LM46002EVM is built for a precision enable application with resistors RENT and
RENB pre-assembled. The regulator will be enabled when VIN > 3.5 V. This threshold can be
calculated by:
2
LM46002EVM User’s Guide
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Setup
Enable _ Voltage
where
•
§
RENT
·
VIH _ EN
¨
1
¸
©
RENB
¹
(1)
VIH_EN is 2.2 V (typ)
PG – Testpoint—
is used to monitor the power good flag. This flag indicates whether the output voltage
has reached its regulation point. This terminal is an open-drain output that requires a pullup resistor
to the appropriate logic voltage (any voltage less than 14 V). A pre-installed resistor RPG1 of 100
kΩ is tied to the PG terminal and brought out to the PG_PULL UP test point.
PG_PULL UP – Testpoint—
is the top connection of the pre-assembled 100-kΩ RPG1 pullup resistor that
ties directly to the open-drain PG terminal. Supply an appropriate voltage to this test point, or tie it
directly to the VOUT test point to observe the PG flag operation.
BIAS – Testpoint—
is used to monitor the BIAS voltage. A pre-installed capacitor of 4.7 µF is connected
from the BIAS terminal to ground (GND). This node is connected to VOUT through a zero Ohm
resistor pre-installed on the bottom layer, labeled (RBIAS).
SYNC – Testpoint —
is the input terminal for an optional external input clock to the converter. The
external clock frequency must be between 200 kHz and 2.2 MHz, if used. A pulldown resistor of
100 kΩ (RSYNC) is installed on the EVM.
SW – Testpoint—
is used to monitor the voltage on the switch terminal and the switching frequency of the
voltage regulator. Remove this test point before making any electromagnetic interference (EMI)
measurements.
VSUPPLY – Edge Connector terminal #9—
is used to supply the input voltage through an on board LC
filter (if one is needed for conducted EMI/EMC measurements). The Lin and Cd component pads
are located on the bottom side of the EVM. Please refer to the EVM schematic for initial suggestion
of component values.
2
Setup
Set the input voltage (VIN) range for the converter between the operating voltage range of 3.5 V to 60 V. If
a load is driven, it should be applied to the VOUT terminal and should not exceed the maximum load
current of 2 A.
3
Operation
For proper operation of the LM46002, VIN, GND, and VOUT should be properly configured as stated
above. In this configuration, the device will start up when power is applied and the output voltage of the
regulator (VOUT) will come up to the proper value. The default setting for output voltage of the
LM46002EVM is 3.3 V. Other output voltages can be set by replacing the feedback terminal resistor
dividers RFBT and RFBB; please consult the datasheet for proper selection of these resistor values.
The default frequency for the LM46002EVM is 500 kHz. If other frequencies are desired, within the
frequency range of 200 kHz and 2.2 MHz, the RT resistor value can be changed. Please consult the
datasheet for proper selection of the RT resistor. You must change inductor (L_60V_HC) and total output
capacitance for proper control loop operation.
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Operation
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Schematic
Figure 2. LM46002EVM Schematic
Board Layout
Figure 3
through
Figure 7
show the board layout for the LM46002EVM. The EVM offers resistors,
capacitors and test points to configure the output voltage, precision enable terminal, set frequency and
external clock synchronization.
The PWP HTSSOP-16 package offers an exposed thermal pad which must be soldered to the copper
landing on the PCB for optimal thermal performance. The PCB consists of a 4-layer design. There are 2-
oz copper planes on the top and bottom and 1-oz copper mid-layer planes to dissipate heat with an array
of thermal vias under the thermal pad to connect to all four layers.
Test points have been provided for ease of use to connect the power supply, required load and to monitor
critical signals. The 12-terminal edge connector can also be used to facilitate the use of a cable harness if
one is required (refer to the
Table 2
section for mating connector part number).
4
LM46002EVM User’s Guide
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Operation
Figure 3. Top Assembly Layer
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LM46002EVM User’s Guide
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