SL23EP04NZ
Low Jitter and Skew DC to 220 MHz Clock Buffer
Key Features
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DC to 220 MHz operating frequency range
Low output clock skew: 60ps-typ
Low part-to-part output skew: 80 ps-typ
3.3V to 2.5V operation supply voltage range
Low power dissipation:
- 10 mA-typ at 66MHz at VDD=3.3V
- 9 mA-typ at 66MHz at VDD=2.5V
One input to four output fanout buffer drivers
Output Enable (OE) control function
Available in 8-pin TSSOP package
Available in Commercial and Industrial grades
Available in Lead (Pb) free package
General Purpose PCI/PCI-X Clock Buffer
Printers, MFPs and Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Datacom and Telecom
High-Speed Digital Embeded Systems
Description
The SL23EP04NZ is a low skew, jitter and power fanout
buffer designed to produce up to four (4) clock outputs
from one (1) reference input clock, for high speed clock
distribution, including PCI/PCI-X applications.
The SL23EP04NZ products operate from DC to 220MHz.
The only difference between SL23EP04-1 and
SL23EP04NZ-1Z is the OE logic implementation. Refer to
the Available OE Logic Configuration Table. 1
Benefits
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Up to four (4) distribution of input clock
Low propagation delay
Low output-to-output skew
Low output jitter
Low power dissipation
Applications
Block Diagram
OE
Logic
Control
CLK1
CLK2
CLKIN
CLK3
CLK4
VDD
GND
Rev 2.1, May 2, 2008
Page 1 of 11
2400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL23EP04NZ
Pin Configuration
CLKIN
OE
CLK1
GND
1
2
3
4
8
7
6
5
CLK4
CLK3
VDD
CLK2
8-Pin TSSOP
Pin Description
Pin
Number
1
2
3
4
5
6
7
8
Pin Name
CLKIN
OE
CLK1
GND
CLK2
VDD
CLK3
CLK4
Pin Type
Input
Output
Output
Power
Output
Output
Power
Input
Reference Clock Input
Pin Description
Output Enable. Refer to the Table. 1 for Logic Table
Buffered Clock Output 1
Power Ground.
Buffered Clock Output 2
3.3V to 2.5V +/-10% Power Supply
Buffered Clock Output 3
Buffered Clock Output 4
Rev 2.1, May 2, 2008
Page 2 of 11
SL23EP04NZ
General Description
The SL23EP04NZ is a low skew, jitter and power fanout
clock distribution buffer designed to produce up to four
(4) clock outputs from one (1) reference input clock, for
high speed clock distribution, including PCI/PCI-X
applications.
Output Clock Skew
All outputs should drive the similar load to achieve output-
to-output skew and input-to-output delay specifications as
given in the switching electrical tables.
Power Supply Range (VDD)
The SL23EP04 is designed to operate from 3.3V+/-10% to
2.5V+/-10% VDD power supply range. An internal on-chip
voltage regulator is used to provide to constant power
supply of 1.8V in the core, leading to a consistent and
stable electrical performance in terms of skew and jitter.
The SL23EP04NZ I/O is powered by using VDD.
Contact SLI for 1.8V power supply Fan-Out Buffer and
ZDB products.
Input and output Frequency Range
The input and output frequency is the same (1x) for
SL23EP04NZ-1 and SL23EP04NZ-1Z. The products
operate from DC to 220MHz clock range with up to
30pF output loads at each output.
OE (Output Enable) Function
The only difference between SL23EP04-1 and
SL23EP04NZ-1Z is the OE logic implementation. When
OE=0, SL23EP04NZ-1 outputs are disabled and outputs
are at Logic Low. In the case of SL23EP04NZ-1Z the
outputs are at High-Z. Refer to the Available OE Logic
Configuration Table. 1 below.
CLKIN (Pin-1)
Low
High
Low
High
OE (Pin-2)
Low
Low
High
High
SL2304NZ-1
CLKOUT [1:4]
Low
Low
Low
High
SL2304NZ-1Z
CLKOUT [1:4]
High-Z
High-Z
Low
High
Table 1. Available SL23EP04 CLKIN and OE Logic Configurations
Rev 2.1, May 2, 2008
Page 3 of 11
SL23EP04NZ
Absolute Maximum Ratings (All Products)
Description
Supply voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
ESD Rating (Human Body Model)
ESD Rating (Charge Device Model)
ESD Rating (Machine Model)
JEDEC22-A114D
JEDEC22-C101C
JEDEC22-A115D
In operation, C-Grade
In operation, I-Grade
No power is applied
In operation, power is applied
Condition
Min
-0.5
-0.5
0
-40
-65
–
–
-4,000
-1,500
-250
Max
4.2
VDD+0.5
70
85
150
125
260
4,000
1,500
250
Unit
V
V
°C
°C
°C
°C
°C
V
V
V
Operating Conditions (C and I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF
Description
Operating Voltage
Symbol
VDD1
TA-1
Condition
VDD+/-10%
Ambient Temperature
C-Grade
Ambient Temperature
I-Grade
Pins 1 and 2
All Outputs≤220MHz,
3.3V
All Outputs≤134MHz,
3.3V
Input Clock Range, CL=15pF
Input Clock Range, CL=30pF
Min
2.97
0
-40
–
–
–
DC
DC
Typ
3.3
–
–
3
–
–
–
–
Max
3.63
70
85
5
15
30
220
134
Unit
V
°C
°C
pF
pF
pF
MHz
MHz
Operating Temperature
TA-2
Input Capacitance
Load Capacitance
VINC
CL1
CL2
Operating Frequency
Operating Frequency
FCLKIN1
FCLKIN2
Rev 2.1, May 2, 2008
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SL23EP04NZ
DC Electrical Characteristics (C-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Power Supply Current
Power Supply Current
Power Supply Current
Symbol
VINL
VINH
IINL
IINH
VOL
VOH
IDD1
IDD2
IDD3
Condition
CLKIN and OE
CLKIN and OE
0 < VIN < 0.8V
2.4V < VIN < VDD
I
OL
=12mA
I
OH
=-12mA
CLKIN=33MHz
CL=0 (No load at outputs)
CLKIN=66MHz
CL=0 (No load at outputs)
CLKIN=166MHz
CL=0 (No load at outputs)
Min
–
2.0
–
–
–
2.4
–
–
–
Typ
–
–
–
–
–
–
8
10
14
Max
0.8
VDD+0.3
10
15
0.4
–
12
15
20
Unit
V
V
µA
µA
V
V
mA
mA
mA
Switching Electrical Characteristics (C-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Output Frequency Range
FOUT2
Input Duty Cycle
Output Duty Cycle
Output Duty Cycle
Output Rise/Fall Time
Output Rise/Fall Time
Output to Output Skew
Part to Part Skew
DC1
DC2
DC3
tr/f-1
tr/f-2
SKW1
SKW2
CL=30pF
Measured at VDD/2
CL=15pF, Fout=166MHz
Measured at VDD/2
CL=30pF, Fout=100MHz
Measured at VDD/2
CL=15pF, measured at 0.8V to 2.0V
CL=30pF, measured at 0.8V to 2.0V
Measured at VDD/2 and
Outputs are equally loaded
Measured at VDD/2 and
Outputs are equally loaded
Measured at VDD/2 from CLKIN to
Output Clock rising edge and Outputs
are equally loaded
CLKIN=66MHz and CL=0 (No Load)
CLKIN=166MHz and CL=0 (No Load)
Power-up time for VDD to reach
maximum specified time
0
20
45
40
–
–
–
–
-
50
50
50
–
–
60
80
134
80
55
60
1.2
1.6
120
160
MHz
%
%
%
ns
ns
ps
ps
Symbol
FOUT1
CL=15pF
Condition
Min
0
Typ
-
Max
220
Unit
MHz
Propagation Delay Time
Cycle-to-Cycle Jitter
Cycle-to-Cycle Jitter
Power-up Time
PDT
CCJ1
CCJ2
tpu
1.5
–
–
0.05
2.5
35
25
–
3.5
70
50
100
ns
ps
ps
ms
Rev 2.1, May 2, 2008
Page 5 of 11
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