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SL23EP09SI-1T

Description
23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
Categorysemiconductor    logic   
File Size142KB,14 Pages
ManufacturerSILABS
Websitehttp://www.silabs.com
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SL23EP09SI-1T Overview

23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

SL23EP09SI-1T Parametric

Parameter NameAttribute value
Number of functions2
Number of terminals16
Minimum operating temperature0.0 Cel
Maximum operating temperature70 Cel
Rated supply voltage2.5
Minimum supply/operating voltage2.3 V
Maximum supply/operating voltage2.7 V
Processing package description4.40 MM, ROHS COMPLIANT, TSSOP-16
EU RoHS regulationsYes
stateActive
Logic IC typeCLOCK DRIVER
series23EP
Max-Min frequency10 MHz
Enter conditionsMUX
jesd_30_codeR-PDSO-G16
moisture_sensitivity_levelNOT SPECIFIED
Number of inverted outputs0.0
Real output number4
Output characteristics3-STATE
Packaging MaterialsPLASTIC/EPOXY
ckage_codeTSSOP
packaging shapeRECTANGULAR
Package SizeSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
eak_reflow_temperature__cel_NOT SPECIFIED
qualification_statusCOMMERCIAL
Maximum same-side bending0.1100 ns
seated_height_max1.1 mm
surface mountYES
Temperature levelCOMMERCIAL
terminal coatingNOT SPECIFIED
Terminal formGULL WING
Terminal spacing0.6500 mm
Terminal locationDUAL
ime_peak_reflow_temperature_max__s_NOT SPECIFIED
length4.4 mm
width3 mm
dditional_featureALSO OPERATES WITH 3.3V SUPPLY
SL23EP09
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
10 to 220 MHz operating frequency range
Low output clock skew: 45ps-typ
Low output clock jitter:
50 ps-typ cycle-to-cycle jitter
20 ps-typ period jitter
Low part-to-part output skew: 90 ps-typ
Wide 2.5 V to 3.3 V power supply range
Low power dissipation:
26 mA-max at 66 MHz and VDD=3.3 V
24 mA-max at 66 MHz and VDD=2.5V
One input drives 9 outputs organized as 4+4+1
Select mode to bypass PLL or tri-state outputs
SpreadThru™ PLL that allows use of SSCG
Standard and High-Drive options
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Printers, MFPs and Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Digital Embeded Systems
Description
The SL23EP09 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9) clock
outputs from one (1) reference input clock, for high speed
clock distribution applications.
The product has an on-chip PLL which locks to the input
clock at CLKIN and receives its feedback internally from the
CLKOUT pin.
The SL23EP09 has two (2) clock driver banks each with four
(4) clock outputs. These outputs are controlled by two (2)
select input pins S1 and S2. When only four (4) outputs are
needed, four (4) bank-B output clock buffers can be tri-stated
to reduce power dissipation and jitter. The select inputs can
also be used to tri-state both banks A and B or drive them
directly from the input bypassing the PLL and making the
product behave like a Non-Zero Delay Buffer (NZDB).
The high-drive version operates up to 220MHz and 200MHz
at 3.3V and 2.5V power supplies respectively.
Applications
Benefits
Up to nine (9) distribution of input clock
Standard and High-Dirive levels to control impedance
level, frequency range and EMI
Low power dissipation, jitter and skew
Low cost
Block Diagram
Low Power and
Low Jitter
PLL
CLKIN
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
S2
Input Selection
Decoding Logic
S1
CLKB1
CLKB2
CLKB3
2
2
CLKB4
VDD
GND
Rev 2.0, May 12, 2008
Page 1 of 14
2400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
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