SI5320 datasheet, PDF - EEWORLD Datasheet

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SI5320: DescriptionSONET/SDH PRECISION CLOCK MULTIPLIER IC; File Size1MB，34 Pages; ManufacturerSILABS; Websitehttp://www.silabs.com

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SI5320 Overview

SONET/SDH PRECISION CLOCK MULTIPLIER IC

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Si5320

SONET/SDH P

R E C I S IO N

LOCK

ULTIPLIER

I C

Features



Ultra-low-jitter clock output with

jitter generation as low as

0.3 ps

RMS



No external components

(other than a resistor and

standard bypassing)



Input clock ranges at 19, 39, 78,

155, 311, and 622 MHz

Output clock ranges at 19, 155,

or 622 MHz

Digital hold for loss of input clock

Support for forward and reverse

FEC clock scaling

Selectable loop bandwidth

Loss-of-signal alarm output

Low power

Small size (9x9 mm)

Si5320

Ordering Information:

Applications



See page 29.



SONET/SDH line/port cards



Optical modules

Core switches



Digital cross connects



Terabit routers

Description

The Si5320 is a precision clock multiplier designed to exceed the requirements of

high-speed communication systems, including OC-192/OC-48 and 10 GbE. This

device phase locks to an input clock in the 19, 39, 78, 155, 311, or 622 MHz

frequency range and generates a frequency-multiplied clock output that can be

configured for operation in the 19, 155, or 622 MHz range. Silicon Laboratories’

DSPLL

™

technology delivers all PLL functionality with unparalleled performance

while eliminating external loop filter components, providing programmable loop

parameters, and simplifying design. FEC rates are supported with selectable 255/

238 or 238/255 scaling of the clock multiplication ratios. The Si5320 establishes a

new standard in performance and integration for ultra-low-jitter clock generation. It

operates from a single 3.3 V supply.

Functional Block Diagram

REXT

VSEL33

V DD

GND

Biasing & Supply Regulation

FXDDELAY

CLKIN+

CLKIN–

CAL_ACTV

Signal

Detect

DSPLL

DH_ACTV

Calibration

CLKOUT+

CLKOUT–

FRQSEL[1:0]

RSTN/CAL

VALTIME

LOS

INFRQSEL[2:0]

FEC[1:0]

DBLBW

BWSEL[1:0]

Rev. 2.5 8/08

Si5320

Si5320

ABLE

Section

ONTENTS

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1. DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.6. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3. Pin Descriptions: Si5320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Rev. 2.5

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