SI5334 datasheet, PDF - EEWORLD Datasheet

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SI5334: DescriptionPIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR; File Size1MB，37 Pages; ManufacturerSILABS; Websitehttp://www.silabs.com

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SI5334 Overview

PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

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Si5334

I N

- C

ONTR OLLED

N Y

- F

REQUENCY

, A

- O

UTPUT

U A D

L O C K

ENERATOR

Features



Low-power MultiSynth technology

enables independent, any-frequency

synthesis on four differential output

drivers

Highly-configurable output drivers

support up to four differential outputs

or eight single-ended clock outputs or

a combination of both

Low phase jitter: 0.7 ps RMS typ

High-precision synthesis allows true

0 ppm frequency accuracy on all

outputs

Flexible input reference

crystal: 8 to 30 MHz

input: 5 to 200 MHz



SSTL/HSTL input: 5 to 350 MHz



Differential input: 5 to 710 MHz



CMOS



External



Independent output voltage per driver



1.5,



1.8,

1.8, 2.5, or 3.3 V

2.5, or 3.3 V

Independent core supply voltage

Frequency increment/decrement

feature enables glitchless frequency

adjustments in 1 ppm steps

Phase adjustment on each of the

output drivers with <20 ps steps

SSC on any or all outputs that is

compliant to PCI Express

Optional external feedback mode

allows zero-delay implementation

Loss-of-lock and loss-of-signal alarm

Simple pin control

Small size: 4x4 mm, 24-QFN

Low power: 45 mA core supply typ

Wide temperature range:

–40 to +85 °C

Contact Silicon Labs for custom

versions

IN1



Ordering Information:

See page 32.

Pin Assignments



Independently-configurable outputs

support any frequency or format



LVPECL/LVDS:



HCSL:

Si5334

Transparent Top View

RSVD_GND

CLK0A

CLK0B

VDDO0

VDD

OEB

CLK1A

CLK1B

VDDO1

GND

IN4

IN5

IN6

VDDO2

CLK2A

CLK2B

LOSLOL

VDDO3

CLK3A

VDD

CLK3B

IN7

0.16 to 710 MHz

0.16 to 250 MHz



CMOS: 0.16 to 200 MHz



SSTL/HSTL: 0.16 to 350 MHz

Applications



Ethernet switch/router



PCI Express 2.0/3.0



Broadcast video/audio timing



Processor and FPGA clocking



Any-frequency clock conversion

MSAN/DSLAM/PON

Fibre Channel, SAN

Telecom line cards

1 GbE and 10 GbE

IN2

IN3

Description

The Si5334 is a high performance, low jitter clock generator capable of

synthesizing any frequency on each of the device's four differential output

clocks. The device accepts an external reference clock or crystal and generates

four differential clock outputs, each of which is independently configurable to

any frequency up to 350 MHz and select frequencies to 710 MHz. Using Silicon

Labs' patented MultiSynth technology, each output clock is generated with very

low jitter and zero ppm frequency error. To provide additional design flexibility,

each output clock is independently configurable to support any signal format and

reference voltage. The Si5334 provides low jitter frequency synthesis with

outstanding frequency flexibility in a space-saving 4 x 4 mm QFN package. The

device configuration is factory or field programmed and, upon power up, the

device will begin operation in the predefined configuration without user

intervention. The device supports operation from a 1.8, 2.5, or 3.3 V core supply.

Rev. 1.2

Si5334

Si5334

ABLE

Section

ONTENTS

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2. Crystal/Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3. Zero Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4. Breakthrough MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5. Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6. Output Clock Initial Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.7. Output Clock Phase Increment and Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.8. Output Clock Frequency Increment and Decrement . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.9. R Divider Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.10. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.11. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.12. LOSLOL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.13. Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.14. Factory Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4. Device Pinout by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5. Ordering Information and Standard Frequency Plans . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

5.2. Evaluation Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3. Standard Frequency Plans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1. Si5334 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

9. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Rev. 1.2

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