Si5375
4-PLL A
NY
- F
REQUENCY
P
RECISION
C
LOCK
M
ULTIPLIER
/J
I T T E R
A
TTENUA TOR
Features
Highly integrated, 4–PLL clock
multiplier/jitter attenuator
Four independent DSPLLs
support any-frequency synthesis
and jitter attenuation
Four inputs/four outputs
Each DSPLL can generate any
frequency from 2 kHz to
808 MHz from a 2 kHz to
710 MHz input
Ultra-low jitter clock outputs:
350 fs rms (12 kHz– 20 MHz)
and 410 fs rms (50 kHz–80 MHz)
typical
Meets ITU-T G.8251 and
Telcordia GR-253-CORE OC-192
jitter specifications
Integrated loop filter with
programmable bandwidth as low
as 60 Hz
Simultaneous free-run and
synchronous operation
Automatic/manual hitless input
clock switching
Selectable output clock signal
format (LVPECL, LVDS, CML,
CMOS)
LOL and interrupt alarm outputs
I
2
C programmable
Single 1.8 V ±5% or 2.5 V ±10%
operation with high PSRR on-
chip voltage regulator
10x10 mm PBGA
Ordering Information:
See page 48.
Applications
High density any-port, any-
protocol, any-frequency line
cards
ITU-T G.709 OTN custom FEC
10/40/100G
OC-48/192, STM-16/64
1/2/4/8/10G Fibre Channel
GbE/10GbE Synchronous Ethernet
Carrier Ethernet, multi-service
switches and routers
MSPP, ROADM, P-OTS,
muxponders
Description
The Si5375 is a highly-integrated, 4-PLL, jitter-attenuating precision clock
multiplier for applications requiring sub 1 ps jitter performance. Each of the
DSPLL
®
clock multiplier engines accepts an input clock ranging from 2 kHz to
710 MHz and generates an output clock ranging from 2 kHz to 808 MHz. The
device provides virtually any frequency translation combination across this
operating range. For asynchronous, free-running clock generation
applications, the Si5375’s reference oscillator can be used as a clock source
for any of the four DSPLLs. The Si5375 input clock frequency and clock
multiplication ratio are programmable through an I
2
C interface. The Si5375 is
based on Silicon Laboratories' third-generation DSPLL
®
technology, which
provides any-frequency synthesis and jitter attenuation in a highly-integrated
PLL solution that eliminates the need for external VCXO and loop filter
components. Each DSPLL loop bandwidth is digitally-programmable,
providing jitter performance optimization at the application level. The device
operates from a single 1.8 or 2.5 V supply with on-chip voltage regulators with
excellent PSRR. The Si5375 is ideal for providing clock multiplication and
jitter attenuation in high port count optical line cards requiring independent
timing domains.
Rev. 1.0 8/12
Copyright © 2012 by Silicon Laboratories
Si5375
Si5375
Functional Block Diagram
Input Stage
CKIN1P_A
CKIN1N_A
÷ N31
PLL Bypass
Synthesis Stage
Output Stage
Input
Monitor
f
3
DSPLL
®
f
OSC
÷
NC1_HS
PLL Bypass
CKOUT1P_A
CKOUT1N_A
A
÷ N32
÷ N2
PLL Bypass
÷ NC1
CKIN1P_B
CKIN1N_B
÷ N31
Input
Monitor
PLL Bypass
f
3
DSPLL
®
f
OSC
÷
NC1_HS
CKOUT1P_B
CKOUT1N_B
B
÷ N32
÷ N2
PLL Bypass
÷ NC1
CKIN1P_C
CKIN1N_C
÷ N31
Input
Monitor
PLL Bypass
f
3
DSPLL
®
f
OSC
÷
NC1_HS
CKOUT1P_C
CKOUT1N_C
C
÷ N32
÷ N2
PLL Bypass
÷ NC1
CKIN1P_D
CKIN1N_D
÷ N31
Input
Monitor
PLL Bypass
f
3
DSPLL
®
f
OSC
÷
NC1_HS
CKOUT1P_D
CKOUT1N_D
D
÷ N32
÷ N2
RSTL_q
CS_q
Status / Control
÷ NC1
High PSRR
Voltage Regulator
OSC_P/N
VDD_q
GND
SCL
SDA LOL_q IRQ_q
Low Jitter
XO or Clock
2
Rev. 1.0
Si5375
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3. Typical Phase Noise Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. Si5375 Application Examples and Suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.1. Schematic and PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2. Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3. SCL Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4. RSTL_x Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5. Reference Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.7. OSC_P and OSC_N Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
7.1. ICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8. Pin Descriptions: Si5375 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
11. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.1. Si5375 Top Marking (PBGA, Lead-Free) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.2. Top Marking Explanation (PBGA, Lead-Free) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.3. Si5375 Top Marking (PBGA, Lead-Finish) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
12.4. Top Marking Explanation (PBGA, Lead-Finish) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Rev. 1.0
3
Si5375
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Supply Voltage during
Normal Operation
Symbol
T
A
2.5 V Nominal
V
DD
1.8 V Nominal
Test Condition
Min
–40
2.25
1.71
Typ
25
2.5
1.8
Max
85
2.75
1.89
Unit
°C
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
SIGNAL +
Differential I/Os V , V
OCM
ICM
SIGNAL –
V
V
ISE
, V
OSE
Single-Ended
Peak-to-Peak Voltage
(SIGNAL +) – (SIGNAL –)
V
ID
,V
OD
V
ICM
, V
OCM
t
Differential Peak-to-Peak Voltage
SIGNAL +
V
ID
= (SIGNAL+) – (SIGNAL–)
SIGNAL –
Figure 1. Differential Voltage Characteristics
80%
CKIN, CKOUT
20%
t
F
t
R
Figure 2. Rise/Fall Time Characteristics
4
Rev. 1.0
Si5375
Table 2. DC Characteristics
(V
DD
= 1.8 ± 5%, 2.5 ±10%, T
A
= –40 to 85 °C)
Parameter
Symbol
Test Condition
LVPECL Format
622.08 MHz Out
All CKOUTs Enabled
Min
—
Typ
870
Max
980
Unit
mA
Supply Current
1
I
DD
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
Disable Mode
—
—
780
660
880
—
mA
mA
CKINn Input Pins
2
Input Common Mode
Voltage (Input Thresh-
old Voltage)
Input Resistance
Single-Ended Input
Voltage Swing
(See Absolute Specs)
1.8 V ± 5%
V
ICM
CKN
RIN
2.5 V ± 10%
Single-ended
f
CKIN
< 212.5 MHz
See Figure 1.
V
ISE
f
CKIN
> 212.5 MHz
See Figure 1.
f
CKIN
< 212.5 MHz
See Figure 1.
V
ID
f
CKIN
> 212.5 MHz
See Figure 1.
0.9
1
20
0.2
0.25
0.2
0.25
—
—
40
—
—
—
—
1.4
1.7
60
—
—
—
—
V
V
k
V
PP
V
PP
V
PP
V
PP
Differential Input
Voltage Swing
(See Absolute Specs)
Output Clocks (CKOUTn)
3,4
Common Mode
Differential Output
Swing
Single Ended Output
Swing
Differential Output
Voltage
Common Mode Output
Voltage
CKO
VCM
CKO
VD
CKO
VSE
CKO
VD
CKO
VCM
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
CML 100
load
line-to-line
CML 100
load
line-to-line
V
DD
–
1.42
1.1
0.5
350
—
—
—
—
425
V
DD
–0.36
V
DD
–1.25
1.9
0.93
500
—
V
V
PP
V
PP
mV
PP
V
Notes:
1.
Current draw is independent of supply voltage.
2.
No under- or overshoot is allowed.
3.
LVPECL outputs require nominal V
DD
= 2.5 V.
4.
LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Rev. 1.0
5
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