PRELIMINARY DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC8158K
RF UP-CONVERTER WITH AGC FUNCTION + IF QUADRATURE MODULATOR IC
FOR DIGITAL MOBILE COMMUNICATION SYSTEMS
DESCRIPTION
The
µ
PC8158K is a silicon microwave monolithic integrated circuit designed as quadrature modulator for digital
mobile communication systems. This MMIC consists of 0.8 GHz to 1.5 GHz up-converter and 100 MHz to 300 MHz
quadrature modulator which are equipped with AGC and power save functions.
NEC’s.
This configuration suits to IF
Consequently the
modulation system. The package is 28-pin QFN suitable for high density mounting. The chip is manufactured using
20 GHz f
T
silicon bipolar process NESAT
TM
III to realize low power consumption.
µ
PC8158K can contribute to make RF blocks smaller size, higher performance and lower power consumption.
FEATURES
•
•
•
•
•
Supply voltage: V
CC
= 2.7 to 4.0 V, I
CC
= 28 mA @ V
CC
= 3.0 V
Built-in LPF suppresses spurious multipled by TX local (LO1)
AGC amplifier is installed in local port of up converter: GCR = 35 dB MIN. @ fout = 1.5 GHz
Excellent performance: P
adj
= –65 dBc TYP. @
∆
f =
±50
kHz, EVM = 1.2 % rms TYP.
External IF filter can be applied between modulator output and up converter input terminal.
APPLICATIONS
• Digital cellular phones (PDC800M, PDC1.5G and so on)
ORDERING INFORMATION
Part Number
Package
28-pin plastic QFN
(5.1
×
5.5
×
0.95 mm)
Embossed tape 12 mm wide.
Pin 1 is in pull-out direction.
QTY 2.5 kp/Reel.
Supplying Form
µ
PC8158K-E1
Remark
To order evaluation samples, please contact your local NEC sales office. (Part number for sample order:
µ
PC8158K)
Caution
Electro-static sensitive device
The information in this document is subject to change without notice.
Document No. P13831EJ1V1DS00 (1st edition)
Date Published January 1999 N CP(K)
Printed in Japan
©
1998
µ
PC8158K
INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (TOP View)
QMOD + AGC + Up-Mix
QMOD + AGC + Up-Mix
QMOD + AGC + Up-Mix
Output Buffer
V
PS
/V
AGC
GND
GND
GND
N.C.
22
21
20
19
AGCcont
18
N.C.
17
16
15
RF
out
23
Up-Mix
N.C.
V
CC
14
LO2inb
N.C.
V
CC
Output Buffer
24
AGC
25
LPF
REG
13
LO2in
GND
QMOD + AGC + Up-Mix
12
Fil1
26
REG
11
V
CC
QMOD + AGC + Up-Mix
LO1in
Fil2
27
10
φ
GND
28 I/Q-Mix
QMOD + AGC + Up-Mix
Phase
Shifter
1
2
3
4
5
6
7
8
9
LO1inb
Qinb
N.C.
N.C.
N.C.
2
Preliminary Data Sheet P13831EJ1V1DS00
N.C.
Iinb
Qin
Iin
µ
PC8158K
QUADRATURE MODULATOR SERIES
f
LO1in
(MHz)
f
MODout
(MHz)
50 to 150
Up-Converter Phase
f
RFout
(MHz) Shifter
External
900 to 1 900
F/F
Doubler
+ F/F
Part Number
Functions
150 MHz Quad. Mod
RF Up-Converter + IF
Quad. Mod
400 MHz Quad. Mod
I
CC
(mA)
Package
20-pin
SSOP (225 mil)
Application
CT-2, etc.
Digital
Comm.
µ
PC8101GR
µ
PC8104GR
µ
PC8105GR
µ
PC8110GR
µ
PC8125GR
µ
PC8126GR
µ
PC8126K
µ
PC8129GR
15/@ 2.7 V 100 to 300
28/@ 3.0 V
100 to 400
16/@ 3.0 V
100 to 400
External
16-pin
SSOP (225 mil)
20-pin
SSOP (225 mil)
PDC800 MHz,
etc.
PHS
1GHz Direct Quad. Mod
24/@ 3.0 V
800 to 1 000
Direct
RF Up-Converter + IF
Quad. Mod + AGC
900 MHz Direct Quad.
Mod with Offset-Mixer
×2LO
IF Quad. Mod +
RF Up-Converter
36/@ 3.0 V
220 to 270
1 800 to 2 000
35/@ 3.0 V
915 to 960
889 to 960
915 to 960
(LO pre-mixer)
800 to 1900
F/F
PDC800 MHz
28-pin QFN
20-pin
SSOP (225 mil)
30-pin
TSSOP
(225 mil)
28-pin QFN
GSM,
DCS1800, etc.
PHS
28/@ 3.0 V 200 to 800 100 to 400
µ
PC8139GR-7JH Transceiver IC
(1.9 GHz Indirect Quad.
Mod + RX-IF + IF VCO)
µ
PC8158K
RF Up-Converter + IF
Quad. Mod + AGC
TX: 32.5
RX: 4.8
/@ 3.0 V
28/@ 3.0 V
220 to 270
1 800 to 2 000
CR
100 to 300
800 to 1 500
PDC800 M/
1.5 G
For outline of the quadrature modulator series, please refer to the application note ‘Usage of
µ
PC8101, 8104,
8105, 8125, 8129’ (Document No. P13251E) and so on.
SYSTEM APPLICATION EXAMPLE
[PDC800 MHz/1.5 GHz]
SUB ANT
LNA
SW
MAIN ANT
1st LO
SW
SW
LO2
AGC
0°
LO1
I
PLL1
PLL2
2nd LO
RSSI
1st MIX
2nd MIX
To DEMOD
RSSI OUT
φ
(CR)
PA
90°
Q
Filter
µ
PC8158K
Preliminary Data Sheet P13831EJ1V1DS00
3
µ
PC8158K
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
V
CC
Conditions
Pin11, 20 and 25,
T
A
= +25°C
Pin17, T
A
= +25°C
Note
Rating
5.0
Unit
V
Power Save and AGC Control Pin
Applied Voltage
Power Dissipation
Operating Ambient Temperature
Storage Temperature
V
PS
/V
AGC
5.0
V
P
D
T
A
T
stg
T
A
= +85°C
430
–40 to +85
–55 to +150
mW
°C
°C
Note
Mounted on double sided copper clad 50
×
50
×
1.6 mm epoxy glass PWB.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Power Save Voltage
AGC Control Voltage
Operating Ambient Temperature
Up-converter RF Output Frequency
LO2 Input Frequency
I/Q Input Frequency
Symbol
V
CC
V
PS
V
AGCPS
T
A
f
RFout
f
LO2in
f
I/Qin
P
LO2in
= –15 dBm
V
I/Qin
= 500 mV
P-P
MAX.
(Differential input)
Test Conditions
Pin11, 20 and 25
Pin17
Pin17
MIN.
2.7
0
1.0
–30
800
600
DC
TYP.
3.0
–
–
+25
–
–
–
MAX.
4.0
0.3
2.5
+80
1500
1750
10
Unit
V
V
V
°C
MHz
MHz
MHz
LO1 Input Level
LO2 Input Level
I/Q Input Amplitude
Up-converter Input Frequency
Modulator Output Frequency
LO1 Input Frequency
P
LO1in
P
LO2in
V
I/Qin
f
UPCONin
f
MODout
f
LO1in
P
LO1in
= –15 dBm
I, Ib, Q, Qb each
–18
–18
–
100
–15
–15
420
–
–12
–12
500
300
dBm
dBm
mV
P-P
MHz
4
Preliminary Data Sheet P13831EJ1V1DS00
µ
PC8158K
ELECTRICAL CHARACTERISTICS
Conditions (Unless otherwise specified):
T
A
= +25 °C, V
CC
1 = V
CC
2
=
V
CC
3 = 3.0 V, V
PS
/V
AGC
= 2.5 V,
I/Q (DC) = Ib/Qb (DC) = V
CC
/2 = 1.5 V, V
I/Ibin
= V
Q/Qbin
= 500 mV
P-P
(each), f
I/Qin
= 2.625 kHz,
π/4DQPSK
wave input, transmission rate 42 kbps, filter roll-off
α
= 0.5,
Modulation Pattern: <0000>
f
LO1in
= 178.05 MHz, P
LO1in
= –15 dBm
f
LO2in
= 1619.05 MHz, P
LO2in
= –15 dBm
f
RFout
= 1441 MHz – f
I/Qin
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
UP-CONVERTER + QUADRATURE MODULATOR TOTAL
Total Circuit Current
Total Circuit Current at Power Save Mode
I
CC (TOTAL)
I
CC (PS) TOTAL
No input signal
V
PS
≤
0.5 V (Low),
No input signal
V
AGC
= 2.5 V
V
AGC
= 1.0 V
f
LOL
= f
LO1
+ f
LO2
23.7
–
28
0.3
37.6
10
mA
µ
A
dBm
dBm
dBc
dBc
dBc
dB
%rms
dBc
Total Output Power 1
Total Output Power 2
LO Carrier Leak
Image Rejection (Side Band Leak)
I/Q 3rd order distortion
AGC Gain Control Range
Error Vector Magnitude
Adjacent channel interference
P
RFout
1
P
RFout
2
LOL
ImR
IM
3 (I/Q)
GCR
EVM
P
adj
–15
–56.5
–
–
–
–11.5
–52
–40
–40
–50
40
1.2
–65
–8
–46.5
–30
–30
–30
–
3.0
–60
V
AGC
= 2 V
→
1 V
MOD Pattern: PN9
35
–
–
Note
∆
f =
±50
kHz,
MOD Pattern: PN9
fLO1
×
8, fLO1
×
8 (image)
V
PS (Low)
→
V
PS (High)
V
PS (High)
→
V
PS (Low)
Between pin I/Ib, Q/Qb
Between pin I/Ib, Q/Qb
f
LO1
= 100 M to 300 MHz
Spurious suppression
Power Save Rise Time
Power Save Fall Time
I/Q input impedance
I/Q input bias current
LO1 input VSWR
P
out
(8fLO1)
T
PS (Rise)
T
PS (Fall)
Z
I/Q
I
I/Q
Z
LO1
–
–
–
80
–
–
–70
2
2
200
5
1.5:1
–65
5
5
–
13
–
dBc
µ
s
µ
s
kΩ
µ
A
–
Note
Without external LC between Fil1 and Fil2 pin on this frequency conditions.
Spectrum analyzer conditions: VBW = 300 Hz, RBW = 300 Hz.
Remark
Electrical characteristics in this document is described for 1.5 GHz system.
Preliminary Data Sheet P13831EJ1V1DS00
5
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