and differentiation capabil‐ • Up to 38.38 megabits (Mb) of embedded memory
ities
• Variable-precision digital signal processing (DSP) blocks
Increased bandwidth
capacity
Hard processor system
(HPS) with integrated
ARM
®
Cortex
™
-A9
MPCore processor
• Serial data rates up to 12.5 Gbps
• Hard memory controllers
• Tight integration of a dual-core ARM Cortex-A9 MPCore processor, hard
IP, and an FPGA in a single Arria V system-on-a-chip (SoC)
• Supports over 128 Gbps peak bandwidth with integrated data coherency
between the processor and the FPGA fabric
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2
Summary of Arria V Features
AV-51001
2020.11.20
Advantage
Supporting Feature
Lowest system cost
• Requires as few as four power supplies to operate
• Available in thermal composite flip chip ball-grid array (BGA) packaging
• Includes innovative features such as Configuration via Protocol (CvP)
and design security
Summary of Arria V Features
Table 2: Summary of Features for Arria V Devices
Feature
Description
Technology
• TSMC's 28-nm process technology:
• Arria V GX, GT, SX, and ST—28-nm low power (28LP) process
• Arria V GZ—28-nm high performance (28HP) process
• Lowest static power in its class (less than 1.2 W for 500K logic elements (LEs) at
85°C junction under typical conditions)
• 0.85 V, 1.1 V, or 1.15 V core nominal voltage
Packaging
• Thermal composite flip chip BGA packaging
• Multiple device densities with identical package footprints for seamless migration
between different device densities
• Leaded
(1)
, lead-free (Pb-free), and RoHS-compliant options
• Enhanced 8-input ALM with four registers
• Improved routing architecture to reduce congestion and improve compilation time
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