DATASHEET
Automotive 5A Synchronous Buck Regulator
ISL78235R5668
The
ISL78235R5668
is a highly efficient, monolithic,
synchronous step-down DC/DC converter that can deliver 5A
continuous and up to 8A pulsed output current from a 2.7V to
5.5V input supply. The device uses peak current mode control
architecture to achieve very low duty cycle operation at high
frequency with fast transient response and excellent loop stability.
The ISL78235R5668 integrates a low ON-resistance P-channel
(35mΩ, typical) high-side FET and N-channel (11mΩ, typical)
low-side FET to maximize efficiency and minimize external
component count. The 100% duty cycle operation allows less
than 250mV dropout voltage at 5A output current. The
operating frequency of the Pulse Width Modulator (PWM) is
adjustable from 500kHz to 4MHz. The default switching
frequency of 2MHz is set by connecting the FS pin high.
The ISL78235R5668 can be configured for discontinuous
(PFM) or forced continuous (PWM) operation at light load.
Forced continuous operation reduces noise and RF
interference, while discontinuous mode provides higher
efficiency by reducing switching losses at light loads.
Fault protection is provided by internal hiccup mode current
limiting during short-circuit and overcurrent conditions. The
device also integrates output overvoltage and
over-temperature protections. A power-good monitor indicates
when the output is in regulation. The ISL78235R5668 offers a
1ms Power-Good (PG) timer at power-up.
When in shutdown, the ISL78235R5668 discharges the output
capacitor through an internal 100Ω soft-stop switch. Other
features include internal fixed or adjustable soft-start and
internal/external compensation.
The ISL78235R5668 is available in a 3mmx3mm 16 Ld Thin
Quad Flat No-lead (TQFN) Pb-free package with an exposed pad
for improved thermal performance. The ISL78235R5668 is
rated to operate across the temperature range of -40°C to
+85°C.
Features
• 2.7 to 5.5V input voltage range
• 5A continuous; 8A pulse output current operation
• 2MHz default switching frequency
• 100ns guaranteed phase minimum on-time for wide output
regulation
• Adjustable switching frequency from 500kHz to 4MHz
• External synchronization from 1MHz to 4MHz
• Optional PFM mode for light-load efficiency improvement
• Very low ON-resistance HS/LS switches: 35mΩ/11mΩ
• Internal 1ms or adjustable external soft-start
• Soft-stop output discharge during disable
• OTP, OCP, output OVP, input UVLO protections
• 1% reference accuracy over-temperature
• Up to 95% efficiency
• AEC-Q100 qualified
Applications
• Automotive infotainment power
• DC/DC point-of-load modules
•
μC/µP,
FPGA and DSP power
• Video processor/SOC power
• Li-ion battery powered devices
Related Literature
•
ISL78235
Datasheet
L
V
OUT
PHASE
PHASE
PHASE
2.7V TO 5.5V
C
IN
VIN
VIN
C
OUT
5A LOAD
DSP, FPGA
100
90
EFFICIENCY (%)
80
70
60
50
40
V
OUT
= 1.2V; T = -40°C
V
OUT
= 1.2V; T = +25°C
V
OUT
= 1.2V; T = +105°C
16
1
15
14
13
12
PGND
PGND
SGND
FB
VDD
2
PG
3
SYNC
4
ISL78235R5668
11
10
9
5
EN
6
FS
7
SS
8
COMP
0
1
2
3
4
5
6
7
8
OUTPUT LOAD (A)
FIGURE 1. TYPICAL APPLICATION: 5A BUCK REGULATOR
FIGURE 2. EFFICIENCY vs LOAD (V
IN
= 5V)
January 21, 2016
FN8769.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78235R5668
Pin Configuration
ISL78235R5668
(16 LD TQFN)
TOP VIEW
PHASE
PHASE
14
PHASE
13
12 PGND
11 PGND
EPAD
10 SGND
9
FB
8
COMP
VIN
16
VIN 1
VDD 2
PG 3
SYNC 4
15
5
EN
6
FS
7
SS
Pin Descriptions
PIN NUMBER
1, 16
2
3
4
PIN NAME
VIN
VDD
PG
SYNC
DESCRIPTION
Input supply voltage. Place a minimum of two 22µF low ESR ceramic capacitors from VIN to PGND as close
as possible to the IC for decoupling.
Input supply voltage for the logic circuitry. A 0.1µF high frequency decoupling ceramic capacitor should also
be placed close to the VDD and SGND pin. Connect to VIN pin.
PG is an open-drain output for power-good indication. Use a 10kΩ to 100kΩ pull-up resistor connected from
PG to VIN. At power-up or EN high, PG rising edge is delayed by 1ms upon output voltage within regulation.
Mode selection pin. Connect to logic high or input voltage VIN for forced PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with a positive edge
trigger. In external synchronization the ISL78235R5668 operates in forced PWM mode. The transition to and
from internal oscillator to external synchronization is seamless and does not require disabling of the
ISL78235R5668. There is an internal 1MΩ pull-down resistor to SGND to prevent an undefined logic state if
SYNC pin is floating.
Regulator enable pin. Regulator is enabled when driven logic high. Regulator is shut down and PHASE pin
discharges the output capacitor when enable pin is driven low.
This pin sets the internal oscillator switching frequency using a resistor, R
FS
, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The switching frequency is 2MHz if
FS is connected to VIN.
SS is used to adjust the soft-start time. Connect SS pin to SGND for internal 1ms soft-start time. Connect a
capacitor from SS to SGND to adjust the soft-start time. Do not use more than 33nF on the SS pin.
COMP is the output of the error amplifier if COMP is not connected to VDD. An external compensation
network must be used if COMP is not tied to VDD. If COMP is tied to VDD, the error amplifier output is
internally compensated. External compensation network across COMP and SGND may be required to
improve the loop compensation of the amplifier.
The feedback network of the regulator, FB, is the negative input to the transconductance error amplifier. The
output voltage is set by an external resistor divider connected to FB. With a properly selected divider, the
output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V
reference. In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the
regulator output voltage.
Analog signal ground. Connect to PGND.
Power ground.
Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω
resistor when the device is disabled. See
“Functional Block Diagram” on page 2
for more detail.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many vias
as possible under the pad connecting to SGND plane for optimal thermal performance.
5
6
EN
FS
7
8
SS
COMP
9
FB
10
11, 12
13, 14, 15
Exposed Pad
SGND
PGND
PHASE
EPAD
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FN8769.1
January 21, 2016
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