UT9Q512K32E datasheet, PDF - EEWORLD Datasheet

Standard Products

UT9Q512K32E 16 Megabit RadTolerant SRAM MCM

Data Sheet

June 28, 2011

FEATURES



25ns maximum (5 volt supply) address access time



Asynchronous operation for compatible with industry

standard 512K x 8 SRAMs



TTL compatible inputs and output levels, three-state

bidirectional data bus



Operational environment:

- Total dose: 50 krads(Si)

- SEL Immune >110 MeV-cm

2

/mg

- LET

TH

(0.25) = >52 MeV-cm

2

/mg

- Saturated Cross Section (cm

2

) per bit, 2.8E-8

- <1.1E-9 errors/bit-day, Adams 90% geosynchronous

heavy ion



Packaging:

- 68-lead dual cavity ceramic quad flatpack (CQFP)

(11.0 grams)



Standard Microcircuit Drawing 5962-01511

- QML Q and Vcompliant part

INTRODUCTION

The UT9Q512K32E RadTol product is a high-performance 2M

byte (16Mbit) CMOS static RAM multi-chip module (MCM),

organized as four individual 524,288 x 8 bit SRAMs with a

common output enable. Memory expansion is provided by an

active LOW chip enable (En), an active LOW output enable (G),

and three-state drivers. This device has a power-down feature

that reduces power consumption by more than 90% when

deselected.

Writing to each memory is accomplished by taking chip enable

(En) input LOW and write enable (Wn) inputs LOW. Data on

the eight I/O pins (DQ

0

through DQ

7

) is then written into the

location specified on the address pins (A

0

through A

18

). Reading

from the device is accomplished by taking chip enable (En) and

output enable (G) LOW while forcing write enable (Wn) HIGH.

Under these conditions, the contents of the memory location

specified by the address pins will appear on the I/O pins.

The input/output pins are placed in a high impedance state when

the device is deselected (En HIGH), the outputs are disabled (G

HIGH), or during a write operation (En LOW and Wn LOW).

Perform 8, 16, 24 or 32 bit accesses by making Wn along with

En a common input to any combination of the discrete memory

die.

E3

A(18:0)

G

W3

E2

W2

E1

W1

W0

E0

512K x 8

DQ(31:24)

or

DQ3(7:0)

DQ(23:16)

or

DQ2(7:0)

DQ(15:8)

or

DQ1(7:0)

DQ(7:0)

or

DQ0(7:0)

Figure 1. UT9Q512K32E SRAM Block Diagram

1

DEVICE OPERATION

The UT9Q512K32E has three control inputs called Enable 1

(En), Write Enable (Wn), and Output Enable (G); 19 address

inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). En

Device Enable controls device selection, active, and standby

modes. Asserting En enables the device, causes I

DD

to rise to its

active value, and decodes the 19 address inputs to select one of

524,288 words in the memory. Wn controls read and write

operations. During a read cycle, G must be asserted to enable

the outputs.

Table 1. Device Operation Truth Table

G

X

1

X

1

Figure 2. 25ns SRAM Pinout (68)

0

1

0

Data out

Wn

X

0

1

En

1

0

I/O Mode

3-state

Data in

3-state

Mode

Standby

Write

Read

2

Read

NC

A0

A1

A2

A3

A4

A5

E2

V

SS

E3

W0

A6

A7

A8

A9

A10

V

DD

DQ0(0)

DQ1(0)

DQ2(0)

DQ3(0)

DQ4(0)

DQ5(0)

DQ6(0)

DQ7(0)

V

SS

DQ0(1)

DQ1(1)

DQ2(1)

DQ3(1)

DQ4(1)

DQ5(1)

DQ6(1)

DQ7(1)

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

1

2

3

4

5

Top View

6

7

8

9

10

11

12

13

14

15

16

17

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

V

DD

A11

A12

A13

A14

A15

A16

E0

G

E1

A17

W1

W2

W3

A18

NC

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

DQ0(2)

DQ1(2)

DQ2(2)

DQ3(2)

DQ4(2)

DQ5(2)

DQ6(2)

DQ7(2)

V

SS

DQ0(3)

DQ1(3)

DQ2(3)

DQ3(3)

DQ4(3)

DQ5(3)

DQ6(3)

DQ7(3)

PIN NAMES

A(18:0)

DQn(7:0)

En

Address

Data Input/Output

Enable

Wn

G

V

DD

V

SS

Write Enable

Output Enable

Power

Ground

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

READ CYCLE

A combination of Wn greater than V

IH

(min) and En less than

V

IL

(max) defines a read cycle. Read access time is measured

from the latter of Device Enable, Output Enable, or valid address

to valid data output.

SRAM Read Cycle 1, the Address Access in figure 3a, is

initiated by a change in address inputs while the chip is enabled

with G asserted and Wn deasserted. Valid data appears on data

outputs DQ(7:0) after the specified t

AVQV

is satisfied. Outputs

remain active throughout the entire cycle. As long as Device

Enable and Output Enable are active, the address inputs may

change at a rate equal to the minimum read cycle time (t

AVAV

).

SRAM read Cycle 2, the Chip Enable - Controlled Access in

figure 3b, is initiated by En going active while G remains

asserted, Wn remains deasserted, and the addresses remain

stable for the entire cycle. After the specified t

ETQV

is satisfied,

the eight-bit word addressed by A(18:0) is accessed and appears

at the data outputs DQ(7:0).

SRAM read Cycle 3, the Output Enable - Controlled Access in

figure 3c, is initiated by G going active while En is asserted, Wn

is deasserted, and the addresses are stable. Read access time is

t

GLQV

unless t

AVQV

or t

ETQV

have not been satisfied.

2

WRITE CYCLE

A combination of Wn less than V

IL

(max) and En less than

V

IL

(max) defines a write cycle. The state of G is a “don’t care”

for a write cycle. The outputs are placed in the high-impedance

state when either G is greater than V

IH

(min), or when Wn is less

than V

IL

(max).

Write Cycle 1, the Write Enable-controlled Access is defined by

a write terminated by Wn going high, with En still active. The

write pulse width is defined by t

WLWH

when the write is initiated

by Wn, and by t

ETWH

when the write is initiated by En. Unless

the outputs have been previously placed in the high-impedance

state by G, the user must wait t

WLQZ

before applying data to the

nine bidirectional pins DQ(7:0) to avoid bus contention.

Write Cycle 2, the Chip Enable-controlled Access is defined by

a write terminated by the latter of En going inactive. The write

pulse width is defined by t

WLEF

when the write is initiated by

Wn, and by t

ETEF

when the write is initiated by the En going

active. For the Wn initiated write, unless the outputs have been

previously placed in the high-impedance state by G, the user

must wait t

WLQZ

before applying data to the eight bidirectional

pins DQ(7:0) to avoid bus contention.

OPERATIONAL ENVIRONMENT

The UT9Q512K32E SRAM incorporates features which allows

operation in a limited environment.

Table 2. Operational Environment

Design Specifications

1

Total Dose

Heavy Ion

Error Rate

2

50

<1.1E-9

krad(Si)

Errors/Bit-Day

Notes:

1. The SRAM will not latchup during radiation exposure under recommended

operating conditions.

2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of

Aluminum.

3

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to V

SS

)

SYMBOL

V

DD

V

I/O

T

STG

P

D

T

J



JC

I

PARAMETER

DC supply voltage

Voltage on any pin

Storage temperature

Maximum power dissipation

Maximum junction temperature

2

Thermal resistance, junction-to-case

3

DC input current

LIMITS

-0.5 to 7.0V

-65 to +150C

1.0W (per byte)

+150C

10C/W

±

10 mA

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device

at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability and performance.

2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life.

3. Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

V

DD

T

C

V

IN

PARAMETER

Positive supply voltage

Case temperature range

DC input voltage

LIMITS

4.5 to 5.5V

(W) Screen - 40C to 105C

0V to V

DD

4

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

-40C to +105C (V

DD

= 5.0V + 10% for (W) screening)

SYMBOL

V

IH

V

IL

V

OL1

V

OL2

V

OH1

V

OH2

C

IN1

C

IO1

I

IN

I

OZ

PARAMETER

High-level input voltage

Low-level input voltage

Low-level output voltage

High-level output voltage

Input capacitance

Bidirectional I/O capacitance

Input leakage current

Three-state output leakage current

(TTL)

I

OL

= 8mA, V

DD

=4.5V (TTL)

I

OL

= 200A,V

DD

=4.5V (CMOS)

I

OH

= -4mA,V

DD

=4.5V (TTL)

I

OH

= 200A,V

DD

=4.5V (CMOS)



= 1MHz @ 0V



= 1MHz @ 0V

V

IN

= V

DD

and V

SS,

V

DD

= V

DD

(max)

V

O

= V

DD

and V

SS

V

DD

= V

DD

(max)

G = V

DD

(max)

I

OS2, 3

I

DD

(OP)

Short-circuit output current

V

DD

= V

DD

(max), V

O

= V

DD

V

DD

= V

DD

(max), V

O

= 0V

Inputs: V

IL

= 0.8V,

V

IH

= 2.0V

I

OUT

= 0mA

V

DD

= V

DD

(max)

Inputs: V

IL

= 0.8V,

V

IH

= 2.0V

I

OUT

= 0mA

V

DD

= V

DD

(max)

-40C and

Inputs: V

IL

= V

SS

25C

I

OUT

= 0mA

E1 = V

DD

- 0.5, V

DD

= V

DD

(max)

105C

V

IH

= V

DD

- 0.5V

9

mA

-90

90

mA

-2

2.4

3.0

45

25

2

CONDITION

MIN

2.0

0.8

0.4

0.08

MAX

UNIT

V

pF

A

Supply current operating

@ 1MHz

(per byte)

40

mA

I

DD1

(OP)

Supply current operating

@40MHz

(per byte)

70

mA

I

DD2

(SB)

Supply current standby

@0MHz

(per byte)

24

mA

Notes:

* Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019.

1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.

5

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